research-article

Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis

Authors:

Shao-Chun Hung,

Jie-Hong R. JiangAuthors Info & Claims

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

Article No.: 73, Pages 1 - 6

https://doi.org/10.1145/3316781.3317801

Published: 02 June 2019 Publication History

Abstract

Threshold logic circuits are artificial neural networks with their neuron outputs being binarized, thus amenable for efficient, multiplier-free, hardware implementation of machine learning applications. In the reviving threshold logic synthesis, this work lays the foundations of disjoint-support decomposition and extraction operation of threshold logic functions. They lead to a synthesis procedure for interconnect minimization of threshold logic circuits, an important, but not well addressed, objective in both neural network and nanometer circuit designs. Experimental results show that our method can efficiently and effectively reduce interconnect as well as weight/threshold value over highly optimized circuits, thus suitable for implementation using emerging technologies.

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Cited By

Chen YZheng LChang H(2023)Don’t-Care-Based Logic Optimization for Threshold LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.323656042:9(2980-2993)Online publication date: Sep-2023
https://doi.org/10.1109/TCAD.2023.3236560
Zheng LChang HChen YJou J(2021)1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification MethodProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431558(469-474)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431558
Lee NJiang J(2021)Constraint Solving for Synthesis and Verification of Threshold Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301544140:5(904-917)Online publication date: May-2021
https://doi.org/10.1109/TCAD.2020.3015441
Show More Cited By

Index Terms

Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
      2. Combinational synthesis

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cover image ACM Conferences

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

June 2019

1378 pages

ISBN:9781450367257

DOI:10.1145/3316781

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 June 2019

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DAC '19: The 56th Annual Design Automation Conference 2019

June 2 - 6, 2019

NV, Las Vegas, USA

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Cited By

Chen YZheng LChang H(2023)Don’t-Care-Based Logic Optimization for Threshold LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.323656042:9(2980-2993)Online publication date: Sep-2023
https://doi.org/10.1109/TCAD.2023.3236560
Zheng LChang HChen YJou J(2021)1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification MethodProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431558(469-474)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431558
Lee NJiang J(2021)Constraint Solving for Synthesis and Verification of Threshold Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301544140:5(904-917)Online publication date: May-2021
https://doi.org/10.1109/TCAD.2020.3015441
Chen YChang HZheng L(2020)Don’t-Care-Based Node Minimization for Threshold Logic Networks2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218506(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218506

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