Yu Zou
ABSTRACT
Non-stencil kernels with irregular memory access patterns pose unique challenges to achieving high computing performance and hardware efficiency in FPGA high-level synthesis. We present a highly versatile and systematic approach, termed as Graph-Morphing, to constructing a reconfigurable computing engine specifically optimized to perform non-stencil kernel computing. Graph-Morphing achieves significant performance improvement by fragmenting operations across loop iterations and subsequently rescheduling computation and data to maximize overall performance. In experiments, Graph-Morphing achieves 2-13 times performance improvement albeit with significantly more hardware usage. For accelerating non-stencil kernel computing, Graph-Morphing proposes a new research direction.
- Uday Kumar Bondhugula. 2008. Effective automatic parallelization and locality optimization using the polyhedral model. Ph.D. Dissertation. The Ohio State University.Google Scholar
- Alessandro Cilardo and Luca Gallo. 2015. Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning. ACM Trans. Archit. Code Optim. 11 (2015), 45:1--45:25. Google ScholarDigital Library
- Jason Cong, Peng Zhang, and Yi Zou. 2011. Combined loop transformation and hierarchy allocation for data reuse optimization. In Proceedings of the International Conference on Computer-Aided Design. IEEE Press, 185--192. Google ScholarDigital Library
- Guohao Dai, Yuze Chi, Yu Wang, and Huazhong Yang. 2016. Fpgp: Graph processing framework on fpga a case study of breadth-first search. In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 105--110. Google ScholarDigital Library
- Alain Darte and Frédéric Vivien. 1997. Optimal fine and medium grain parallelism detection in polyhedral reduced dependence graphs. International Journal of Parallel Programming 25, 6 (1997), 447--496. Google ScholarDigital Library
- Juan Escobedo and Mingjie Lin. 2017. Tessellating Memory Space for Parallel Access. In ASP-DAC.Google Scholar
- Juan Escobedo and Mingjie Lin. 2018. Extracting Data Parallelism in Non-stencil Kernel Computing by Optimally Coloring Folded Memory Conflict Graph. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 156, 6 pages. Google ScholarDigital Library
- Juan Escobedo and Mingjie Lin. 2018. Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '18). ACM, New York, NY, USA, 199--208. Google ScholarDigital Library
- Paul Feautrier. 1992. Some efficient solutions to the affine scheduling problem. I. One-dimensional time. International journal of parallel programming 21, 5 (1992), 313--347. Google ScholarDigital Library
- Matthew Jacobsen, Dustin Richmond, Matthew Hogains, and Ryan Kastner. 2015. RIFFA 2.1: A reusable integration framework for FPGA accelerators. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8, 4 (2015), 22. Google ScholarDigital Library
- Jialin Ju and Vipin Chaudhary. 1997. Unique sets oriented parallelization of loops with non-uniform dependences. Comput. J. 40, 6 (1997), 322--339.Google ScholarCross Ref
- Ken Kennedy and John R Allen. 2001. Optimizing compilers for modern architectures: a dependence-based approach. Morgan Kaufmann Publishers Inc. Google ScholarDigital Library
- Junyi Liu, John Wickerson, and George A Constantinides. 2016. Loop splitting for efficient pipelining in high-level synthesis. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 72--79.Google ScholarCross Ref
- Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, and Naofumi Takagi. 2013. A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis. In International Conference on Algorithms and Architectures for Parallel Processing. Springer, 390--401. Google ScholarDigital Library
- Yuxin Wang, Peng Li, and Jason Cong. 2014. Theory and Algorithm for Generalized Memory Partitioning in High-level Synthesis. In Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA '14). ACM, New York, NY, USA, 199--208. Google ScholarDigital Library
- Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, and Jason Cong. 2013. Memory partitioning for multidimensional arrays in high-level synthesis. In Proceedings of the 50th Annual Design Automation Conference. ACM, 12. Google ScholarDigital Library
- Xiaowei Zhu, Wentao Han, and Wenguang Chen. 2015. GridGraph: Large-Scale Graph Processing on a Single Machine Using 2-Level Hierarchical Partitioning.. In USENIX Annual Technical Conference. 375--386. Google ScholarDigital Library
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