research-article

LL-PCM: Low-Latency Phase Change Memory Architecture

Authors:

Myoungsoo JungAuthors Info & Claims

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

Article No.: 14, Pages 1 - 6

https://doi.org/10.1145/3316781.3317853

Published: 02 June 2019 Publication History

Abstract

PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/write-driver. This in turn requires (1) a very large charge pump consuming: ~20% of PCM chip space, ~50% of latency of write operations, and ~2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LL-PCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ~1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.

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Index Terms

LL-PCM: Low-Latency Phase Change Memory Architecture
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

June 2019

1378 pages

ISBN:9781450367257

DOI:10.1145/3316781

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 02 June 2019

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DAC '19: The 56th Annual Design Automation Conference 2019

June 2 - 6, 2019

NV, Las Vegas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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https://dl.acm.org/doi/10.1145/3649329.3655968
Akbarzadeh NDarabi SGheibi-Fetrat AMirzaei ASadrosadati MSarbazi-Azad H(2024)H3DM: A High-bandwidth High-capacity Hybrid 3D Memory Design for GPUsProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/36390388:1(1-28)Online publication date: 21-Feb-2024
https://dl.acm.org/doi/10.1145/3639038
Zeng JJeong JJung C(2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623772
Wu SChen LHuang PChang YHo CShih W(2023)WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent MemoriesACM Transactions on Embedded Computing Systems10.1145/360803322:5s(1-26)Online publication date: 31-Oct-2023
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Wang CFeng DTong WLiu J(2023)CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247700(1-6)Online publication date: 9-Jul-2023
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Narayan AThonnart YVivet PCoskun AJoshi A(2022)Architecting Optically Controlled Phase Change MemoryACM Transactions on Architecture and Code Optimization10.1145/353325219:4(1-26)Online publication date: 28-Oct-2022
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