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Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism

Published: 02 June 2019 Publication History

Abstract

Optimizations at placement stage need to be guided by timing estimation prior to routing. To handle timing uncertainty due to the lack of routing information, people tend to make very pessimistic predictions such that performance specification can be ensured in the worst case. Such pessimism causes over-design that wastes chip resources or design effort. In this work, a machine learning-based pre-routing timing prediction approach is introduced. Experimental results show that it can reach accuracy near post-routing sign-off analysis. Compared to a commercial pre-routing timing estimation tool, it reduces false positive rate by about 2/3 in reporting timing violations.

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  1. Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism

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    cover image ACM Conferences
    DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
    June 2019
    1378 pages
    ISBN:9781450367257
    DOI:10.1145/3316781
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 02 June 2019

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    Author Tags

    1. Machine Learning
    2. Pre-routing delay estimation
    3. Static Timing Analysis

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    Cited By

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    • (2024)TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis AccelerationElectronics10.3390/electronics1315289713:15(2897)Online publication date: 23-Jul-2024
    • (2024)The shift-left design paradigm of EDA: progress and challengesSCIENTIA SINICA Informationis10.1360/SSI-2023-031454:1(121)Online publication date: 12-Jan-2024
    • (2024)OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538770(1-4)Online publication date: 22-Apr-2024
    • (2024)DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337011043:8(2493-2506)Online publication date: Aug-2024
    • (2024)Delay Aware Reduced SPEF STA2024 IEEE Symposium on Industrial Electronics & Applications (ISIEA)10.1109/ISIEA61920.2024.10607331(1-6)Online publication date: 6-Jul-2024
    • (2024)AIP-SEM: An Efficient ML-Boost In-Place Soft Error Mitigation Method for SRAM-Based FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617841(351-354)Online publication date: 10-May-2024
    • (2024)An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473937(177-182)Online publication date: 22-Jan-2024
    • (2024)Pre-route timing prediction and optimization with graph neural network modelsIntegration10.1016/j.vlsi.2024.102262(102262)Online publication date: Aug-2024
    • (2023)Near-Threshold Wide-Voltage Design ReviewTsinghua Science and Technology10.26599/TST.2022.901006428:4(696-718)Online publication date: Aug-2023
    • (2023)DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137234(1-6)Online publication date: Apr-2023
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