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Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs

Published: 02 June 2019 Publication History

Abstract

We present an effective methodology for formally verifying security-critical flows in a commercial System-on-Chip (SoC) which involve extensive interaction between firmware (FW) and hardware (HW). We describe several HW-FW interaction scenarios that are typical in commercial SoCs. We highlight unique challenges associated with formal verification of security properties of such interactions and discuss our approach of property-specific abstraction and software model checking to circumvent those challenges. To the best of our knowledge, this is the first exposition on formal co-verification of security-specific HW-FW interactions in the context and scale of a commercial SoCs. Despite traditional scalability challenges, we demonstrate that many such flows are amenable to effective formal verification.

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  • (2024)Theoretical Patchability Quantification for IP-Level Hardware Patching Designs2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473895(951-956)Online publication date: 22-Jan-2024
  • (2024)Hardware/software security co-verification and vulnerability detection: An information flow perspectiveIntegration10.1016/j.vlsi.2023.10208994(102089)Online publication date: Jan-2024
  • (2022)Automating hardware security property generationProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530637(1384-1387)Online publication date: 10-Jul-2022
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  1. Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs

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    cover image ACM Conferences
    DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
    June 2019
    1378 pages
    ISBN:9781450367257
    DOI:10.1145/3316781
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 02 June 2019

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    Author Tags

    1. HW-FW co-verification
    2. Model Checking
    3. System Security

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    View all
    • (2024)Theoretical Patchability Quantification for IP-Level Hardware Patching Designs2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473895(951-956)Online publication date: 22-Jan-2024
    • (2024)Hardware/software security co-verification and vulnerability detection: An information flow perspectiveIntegration10.1016/j.vlsi.2023.10208994(102089)Online publication date: Jan-2024
    • (2022)Automating hardware security property generationProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530637(1384-1387)Online publication date: 10-Jul-2022
    • (2022)Enhancement of Emulation Usage for NVMe Solid State Drive2022 19th International SoC Design Conference (ISOCC)10.1109/ISOCC56007.2022.10031432(382-383)Online publication date: 19-Oct-2022
    • (2021)Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301977240:6(1158-1171)Online publication date: Jun-2021

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