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RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

Published: 02 June 2019 Publication History

Abstract

Monolithic 3D IC overcomes the limitation of the existing through-silicon-via (TSV) based 3D IC by providing denser vertical connections with nano-scale inter-layer vias (ILVs). In this paper, we demonstrate a thorough RTL-to-GDS design flow for monolithic 3D IC, which is based on commercial 2D place-and-route (P&R) tools and clever ways to extend them to handle 3D IC designs and simulations. We also provide a low-cost built-in-self-test (BIST) method to detect various faults that can occur on ILVs. Lastly, we present a resistive random access memory (ReRAM) compiler that generates memory modules that are to be integrated in monolithic 3D ICs.

References

[1]
S. Wong et al., "Monolithic 3D Integrated circuits," in VLSI-TSA, 2007.
[2]
A. Koneru et al., "A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3D Integrated Circuits," in TCAD, 2018.
[3]
C.-C. Chou et al., "An N40 256K×44 Embedded RRAM Macro with SL-precharge SA and Low-voltage Current Limiter to Improve Read and Write Performance," in ISSCC, 2018.
[4]
M. F. Chang et al., "19.4 Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V Read using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme," in ISSCC, 2014.
[5]
S. Panth et al., "Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs," in IEEE Int. Symp. on Low Power Electronics and Design, 2014.
[6]
K. Chang et al., "Cascade2D: A Design-Aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools," in IEEE Int. Conf. on Computer-Aided Design, 2016.
[7]
B. W. Ku, K. Chang, and S. K. Lim, "Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs," in IEEE Int. Symp. on Physical Design, 2018.
[8]
C. M. Fiduccia and R. M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions," in DAC, 1982.
[9]
R. Pendurkar et al., "Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects," in TCAD, 2001.
[10]
A. Jutman, "Shift Register Based TPG for At-Speed Interconnect BIST," in ICM, 2004.
[11]
D. Erb et al., "Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects," in VTS, 2015.
[12]
S.-S. Sheu et al., "A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability," in ISSCC, 2011.
[13]
X. Dong et al., "NVsim: A Circuit-level Performance, Energy, and Area Model for Emerging Nonvolatile Memory," TCAD, 2012.
[14]
H. Li et al., "Variation-Aware, Reliability-Emphasized Design and Optimization of RRAM using SPICE Model," in DATE, 2015.

Cited By

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  • (2023)Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137051(1-6)Online publication date: Apr-2023
  • (2022)Emerging monolithic 3D integrationIntegration, the VLSI Journal10.1016/j.vlsi.2022.04.00485:C(97-107)Online publication date: 1-Jul-2022
  • (2021)Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R ToolElectronics10.3390/electronics1016193010:16(1930)Online publication date: 11-Aug-2021
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  1. RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

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    cover image ACM Conferences
    DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
    June 2019
    1378 pages
    ISBN:9781450367257
    DOI:10.1145/3316781
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 02 June 2019

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    View all
    • (2023)Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137051(1-6)Online publication date: Apr-2023
    • (2022)Emerging monolithic 3D integrationIntegration, the VLSI Journal10.1016/j.vlsi.2022.04.00485:C(97-107)Online publication date: 1-Jul-2022
    • (2021)Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R ToolElectronics10.3390/electronics1016193010:16(1930)Online publication date: 11-Aug-2021
    • (2021)A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube ProcessACM Journal on Emerging Technologies in Computing Systems10.1145/346668118:1(1-20)Online publication date: 3-Nov-2021
    • (2020)Quantifying the benefits of monolithic 3D computing systems enabled by TFT and RRAMProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408362(43-48)Online publication date: 9-Mar-2020
    • (2020)Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116410(43-48)Online publication date: Mar-2020
    • (2020)Advances in Design and Test of Monolithic 3-D ICsIEEE Design & Test10.1109/MDAT.2020.298865737:4(92-100)Online publication date: Aug-2020
    • (2020) NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs ∗ 2020 IEEE 29th Asian Test Symposium (ATS)10.1109/ATS49688.2020.9301589(1-6)Online publication date: 23-Nov-2020
    • (2019)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058793(1-5)Online publication date: Oct-2019

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