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Optimizing Persistent Transactions (Brief Announcement)

Published: 17 June 2019 Publication History

Abstract

There is a mechanical transformation by which algorithms for software transactional memory can be transformed to work with persistent memory. While correct, this transformation does not take into account differences between the persistent and volatile programming models. We show that fundamental properties of the data regions accessed by a persistent software transaction allow for a variety of optimizations not available in the volatile setting, and these lead to significant performance gains.

References

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Joel Coburn et al. 2011. NV-Heaps: Making Persistent Objects Fast and Safe with Next-generation, Non-volatile Memories. In Proceedings of the Sixteenth ASPLOS. New York, NY, USA.
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Mengxing Liu et al. 2017. DudeTM: Building Durable Transactions with Decoupling for Persistent Memory. In Proceedings of the 22nd ASPLOS. Xi'an, China.
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Michael Spear et al. 2008. Implementing and Exploiting Inevitability in Software Transactional Memory. In Proceedings of the 37th ICPP. Portland, OR.
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Michael Spear et al. 2008. RingSTM: Scalable Transactions with a Single Atomic Instruction. In Proceedings of the 20th SPAA. Munich, Germany.
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Pascal Felber et al. 2008. Dynamic Performance Tuning of Word-Based Software Transactional Memory. In Proceedings of the 13th PPoPP. Salt Lake City, UT.
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Richard Yoo et al. 2008. Kicking the Tires of Software Transactional Memory: Why the Going Gets Tough. In Proceedings of the 20th SPAA. Munich, Germany.
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Maurice P. Herlihy and J. Eliot B. Moss. 1993. Transactional Memory: Architectural Support for Lock-Free Data Structures. In Proceedings of the 20th ISCA. San Diego, CA.
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Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, and Kunle Olukotun. 2008. STAMP: Stanford Transactional Applications for Multi-processing. In Proceedings of IISWC. Seattle, WA.
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Newsroom, Intel. 2018. Intel and Micron produce breakthrough memory technology. https://www.intel.com/content/www/us/en/architecture-and-technology/intel-optane-technology.html.
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Haris Volos, Andres Jaan Tack, and Michael M. Swift. 2011. Mnemosyne: Lightweight persistent memory. In ACM SIGARCH Computer Architecture News.

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Published In

cover image ACM Conferences
SPAA '19: The 31st ACM Symposium on Parallelism in Algorithms and Architectures
June 2019
410 pages
ISBN:9781450361842
DOI:10.1145/3323165
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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  • EATCS: European Association for Theoretical Computer Science

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 June 2019

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Author Tags

  1. concurrency
  2. persistence
  3. transactional memory

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  • Announcement

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  • Intel and NSF joint research center for Computer Assisted Programming for Heterogeneous Architectures (CAPA)
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SPAA '19

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SPAA '19 Paper Acceptance Rate 34 of 109 submissions, 31%;
Overall Acceptance Rate 447 of 1,461 submissions, 31%

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SPAA '25
37th ACM Symposium on Parallelism in Algorithms and Architectures
July 28 - August 1, 2025
Portland , OR , USA

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