Nguyen Cao Qui
ABSTRACT
Conventionally, to investigate the aging effects in analog-circuit-design phase, it requires to simulate, modify and verify iteratively on a number of circuit samples. In this work, we propose a fast aging simulation scheme for analog circuit modification and verification process based on the delta model in which the delta circuits are made from the delta devices built with the aging effect models by Verilog-A. During simulation, the aging device parameters are also updated continuously to attain the same accuracy with works in the literature; however, we only simulate the signal-difference between two similar circuits by re-using the previous simulation results to accelerate the aging simulation process. The experiment results show that, in the scenario of channel hot carrier effect on an analog amplifier circuit, the aging simulation process of the proposed scheme can be sped-up 10 times compared to that of conventional scheme with almost the same accuracy.
- Lee, H.-J. and Kim, K.-K. 2011. Analysis of time dependent dielectric Breakdown in Nanoscale CMOS Circuit. In Proceedings of the 2011 International SoC Design Conference (Jeju, South Korea, November 17-18, 2011). ISOCC '11., New York, NY, 440--443.Google Scholar
- Black, J. 1969. Electromigration - A brief survey and some recent results. IEEE Trans. Electron Devices 16, 4 (Apr. 1969), 338--347.Google ScholarCross Ref
- Wang, W., Reddy, V., Krishnan, A. T., Vattikonda, R., Krishnan, S. and Cao, Y. 2007. Compact modeling and simulation of circuit reliability for 65nm CMOS technology. IEEE Trans. Device and Materials Reliability 7, 4 ( Dec. 2007), 509--517.Google Scholar
- Hu, R. T. et. al. 1993. Berkeley Reliability Tools-BERT. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 12, 10 (Oct. 1993), 1524--1534. Google ScholarDigital Library
- Karam, M., Fikry, W., Haddara, H. and Ragai H. 2001. Implementation of hot-carrier reliability simulation in Eldo. In Proceedings of the 2001 IEEE Int'l Symp. Circuits and Systems (Sydney, Australia, May 06-09, 2001). ISCAS '01, New York, NY, 515--518.Google Scholar
- Marc, F., Mongellaz, B., Bestory, C., Levi H., and Danto, Y. 2006. Improvement of aging simulation of electronic circuits using behavioral modeling. IEEE Trans. Device and Materials Reliability 6, 2 (Jun. 2006), 228--234.Google ScholarCross Ref
- Patra, D. et. al. 2017. Adaptive accelerated aging with 28nm HKMG technology. In Proceedings of the 2017 IEEE International Reliability Physics Symposium (Monterey, CA, USA, April 2-6, 2017). IRPS '17, New York, NY, CR-2.1-CR-2.4.Google ScholarDigital Library
- Patra, D. et. al. 2018. Compact modeling and simulation of accelerated circuit aging. In Proceedings of the 2018 IEEE Custom Integrated Circuits Conference (San Diego, CA, USA, April 8-11, 2018). CICC '18., New York, NY, 1--4.Google ScholarCross Ref
- Zhou, T. Y., Liu, H., Zhou, D., and Tarim, T. 2011. A fast analog circuit analysis algorithm for design modification and verification. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 30, 2 (Feb. 2011), 308--313. Google ScholarDigital Library
- Qui, N. C., He, S-R. and Liu C-N. J. 2017. Cluster-Based delta-QMC technique for fast yield analysis. Integration, the VLSI Journal 58 (June 2017), 64--73.Google Scholar
- Qui, N. C., He, S-R. and Liu C-N. J. 2017. An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis. IEICE Trans. Fundamentals E100-A, 11 (Nov. 2017), 2370--2378.Google Scholar
Index Terms
- A Fast Aging Simulation Based On Delta Model For Analog Circuit Modification and Verification
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