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Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Authors:

Irith Pomeranz,

Sudhakar M. Reddy,

Srikanth VenkataramanAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 4

Article No.: 42, Pages 1 - 19

https://doi.org/10.1145/3325066

Published: 29 May 2019 Publication History

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Abstract

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

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Cited By

Zhang QHuang HLi JZhang YLi Y(2022)CmpCNN: CMP Modeling with Transfer Learning CNN ArchitectureACM Transactions on Design Automation of Electronic Systems10.1145/3569941Online publication date: 27-Oct-2022
https://doi.org/10.1145/3569941
Raman SLimpisathian PMeinerzhagen PNatarajan SYang E(2020)Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization2020 IEEE International Test Conference (ITC)10.1109/ITC44778.2020.9325263(1-10)Online publication date: 1-Nov-2020
https://doi.org/10.1109/ITC44778.2020.9325263
Wang HLi JHe K(2019)Hierarchical Ensemble Reduction and Learning for Resource-constrained ComputingACM Transactions on Design Automation of Electronic Systems10.1145/336522425:1(1-21)Online publication date: 4-Dec-2019
https://dl.acm.org/doi/10.1145/3365224

Index Terms

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design
1. Hardware

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 24, Issue 4

July 2019

258 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3326461

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2019 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 May 2019

Accepted: 01 March 2019

Revised: 01 February 2019

Received: 01 October 2018

Published in TODAES Volume 24, Issue 4

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Cited By

Zhang QHuang HLi JZhang YLi Y(2022)CmpCNN: CMP Modeling with Transfer Learning CNN ArchitectureACM Transactions on Design Automation of Electronic Systems10.1145/3569941Online publication date: 27-Oct-2022
https://doi.org/10.1145/3569941
Raman SLimpisathian PMeinerzhagen PNatarajan SYang E(2020)Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization2020 IEEE International Test Conference (ITC)10.1109/ITC44778.2020.9325263(1-10)Online publication date: 1-Nov-2020
https://doi.org/10.1109/ITC44778.2020.9325263
Wang HLi JHe K(2019)Hierarchical Ensemble Reduction and Learning for Resource-constrained ComputingACM Transactions on Design Automation of Electronic Systems10.1145/336522425:1(1-21)Online publication date: 4-Dec-2019
https://dl.acm.org/doi/10.1145/3365224

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