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The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture

Published: 22 June 2019 Publication History

Abstract

Computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.

References

[1]
Sahan Bandara, Alan Ehret, Donato Kava, and Michel Kinsy. 2019. BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '19). ACM, New York, NY, USA, 306--306.
[2]
N. Boskov, M Isakov, and M. A. Kinsy. 2019. CodeTrolley: Hardware-Assisted Control Flow Obfuscation. Boston Area Architecture 2019 Workshop (BARC19) (Jan. 2019). arXiv:1903.00841
[3]
Michael Graziano, Miguel Mark, Stefan Gvozdenovic, and Michel A. Kinsy. 2019. Hardware Assisted Transparent ROP Mitigation for RISC-V. Boston Area Architecture 2019 Workshop (BARC19) (Jan. 2019).
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Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. 2005. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '05). ACM, New York, NY, USA, 190--200.
[5]
A Waterman and K Asanovic. 2017. The RISC-V Instruction Set Manual-Volume I: User-Level ISA-Document Version 2.2. RISC-V Foundation (May 2017) (2017).

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  • (2024)MiniJava on RISC-V: A Game of Global Compilers DominationProceedings of the Workshop Dedicated to Jens Palsberg on the Occasion of His 60th Birthday10.1145/3694848.3694854(21-29)Online publication date: 22-Oct-2024
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Published In

cover image ACM Conferences
WCAE'19: Proceedings of the Workshop on Computer Architecture Education
June 2019
70 pages
ISBN:9781450368421
DOI:10.1145/3338698
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 June 2019

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Author Tags

  1. Verilog
  2. computer architecture
  3. computer organization
  4. generator
  5. risc-v
  6. simulator

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ISCA '19
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Overall Acceptance Rate 9 of 10 submissions, 90%

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Cited By

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  • (2025)VRV: A Versatile RISC-V Simulator for EducationProceedings of the 56th ACM Technical Symposium on Computer Science Education V. 210.1145/3641555.3705240(1505-1506)Online publication date: 18-Feb-2025
  • (2025)ASM Visualizer: A Learning Tool for Assembly ProgrammingProceedings of the 56th ACM Technical Symposium on Computer Science Education V. 110.1145/3641554.3701793(840-846)Online publication date: 12-Feb-2025
  • (2024)MiniJava on RISC-V: A Game of Global Compilers DominationProceedings of the Workshop Dedicated to Jens Palsberg on the Occasion of His 60th Birthday10.1145/3694848.3694854(21-29)Online publication date: 22-Oct-2024
  • (2024)An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture EducationIEEE Revista Iberoamericana de Tecnologias del Aprendizaje10.1109/RITA.2024.345885019(176-185)Online publication date: 2024
  • (2024)RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558557(1-5)Online publication date: 19-May-2024
  • (2023)A Practical Computer Architecture Education with RISC-V and TL-Verilog2023 XXXII International Scientific Conference Electronics (ET)10.1109/ET59121.2023.10279744(1-6)Online publication date: 13-Sep-2023
  • (2022)Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to MicrocontrollersJournal of Low Power Electronics and Applications10.3390/jlpea1203004512:3(45)Online publication date: 9-Aug-2022
  • (2022)LY86-64Proceedings of the 2022 ACM Southeast Conference10.1145/3476883.3520224(31-37)Online publication date: 18-Apr-2022
  • (2022)CPU Execution Time Analysis based on RISC-V ISA Simulators: A Survey2022 International Conference on Development and Application Systems (DAS)10.1109/DAS54948.2022.9786163(12-18)Online publication date: 26-May-2022
  • (2021)SimpliFI: Hardware Simulation of Embedded Software Fault AttacksCryptography10.3390/cryptography50200155:2(15)Online publication date: 7-Jun-2021
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