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A new algorithm for an incremental sigma-delta converter reconstruction filter

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Published:26 August 2019Publication History

ABSTRACT

Image sensors dedicated for the applications of the Earth observation require medium-speed and high-resolution analog-to-digital converters (ADCs). For that purpose, an incremental sigma-delta analog-to-digital converter (IΣΔ ADC) has been designed. Post-layout simulations highlighted a degradation in resolution caused by the circuit imperfections. Therefore, a digital correction has been investigated. This paper proposes a new reconstruction filter which takes into account not only the bit values of the modulator output sequence but also the occurrence of certain patterns. This technique has been applied to an incremental sigma-delta analog-to-digital converter in order to correct the conversion errors. Performing with 400 clock periods for each conversion cycle, the theoretical resolution is 15.4 bits. Post-layout simulation shows that a 13.5-bit resolution is obtained by using the classical optimal filter whereas a 14.8-bit resolution is obtained with our reconstruction filter.

References

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        cover image ACM Conferences
        SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design
        August 2019
        204 pages
        ISBN:9781450368445
        DOI:10.1145/3338852

        Copyright © 2019 ACM

        © 2019 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 26 August 2019

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