research-article

Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform

Authors:

Tsung-Chun Lin,

Wuu YangAuthors Info & Claims

ICPP Workshops '19: Workshop Proceedings of the 48th International Conference on Parallel Processing

Article No.: 12, Pages 1 - 7

https://doi.org/10.1145/3339186.3339192

Published: 05 August 2019 Publication History

Abstract

Binary translation translates binary programs from one instruction set to another. It is widely used in virtual machines and emulators. We extend mc2llvm, which is an LLVM-based retargetable 32-bit binary translator developed in our lab in the past several years, to support 64-bit ARM instruction set. In this paper, we report the translation of AArch64 floating-point instructions in our mc2llvm. For floating-point instructions, due to the lack of floating-point support in LLVM [13, 14], we add support for the flush-to-zero mode, not-a-number processing, floating-point exceptions, and various rounding modes. On average, mc2llvm-translated binary can achieve 47% and 24.5% of the performance of natively compiled x86-64 binary on statically translated EEMBC benchmark and dynamically translated SPEC CINT2006 benchmarks, respectively. Compared to QEMU-translated binary, mc2llvm-translated binary runs 2.92x, 1.21x and 1.41x faster on statically translated EEMBC benchmark, dynamically translated SPEC CINT2006, and CFP2006 benchmarks, respectively. (Note that the benchmarks contain both floating-point instructions and other instructions, such as load and store instructions.)

References

[1]

{n. d.}. musl. https://www.musl-libc.org/

[2]

2008. IEEE Standard for Floating-Point Arithmetic. IEEE Std 754-2008 (Aug 2008), 1--70.

[3]

ARM 2013. ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. ARM.

[4]

Fabrice Bellard. 2005. QEMU, a Fast and Portable Dynamic Translator. In Proceedings of the Annual Conference on USENIX Annual Technical Conference (ATEC '05). USENIX Association, Berkeley, CA, USA, 41--41. http://dl.acm.org/citation.cfm?id=1247360.1247401

Digital Library

[5]

Jiunn-Yeu Chen, Wuu Yang, Wei-Chung Hsu, Bor-Yeh Shen, and Quan-Huei Ou. 2017. On Static Binary Translation of ARM/Thumb Mixed ISA Binaries. ACM Trans. Embed. Comput. Syst. 16, 3, Article 81 (March 2017), 25 pages.

Digital Library

[6]

Jiunn-Yeu Chen, Wuu Yang, Bor-Yeh Shen, Yuan-Jia Li, and Wei-Chung Hsu. 2015. Automatic Validation for Binary Translation. Comput. Lang. Syst. Struct. 43, C (Oct. 2015), 96--115.

Digital Library

[7]

T. J. Dekker. 1971. A floating-point technique for extending the available precision. Numer. Math. 18, 3 (1971), 224--242.

Digital Library

[8]

Yu-Chuan Guo, Wuu Yang, Jiunn-Yeu Chen, and Jenq-Kuen Lee. 2016. Translating the ARM Neon and VFP instructions in a binary translator. Software: Practice and Experience 46, 12 (2016), 1591--1615.

Digital Library

[9]

John R. Hauser. 1996. Handling Floating-point Exceptions in Numeric Programs. ACM Trans. Program. Lang. Syst. 18, 2 (March 1996), 139--174.

Digital Library

[10]

John R. Hauser. 2018. Berkeley SoftFloat. http://www.jhauser.us/arithmetic/SoftFloat.html.

[11]

John R. Hauser. 2018. Berkeley SoftFloat Release 3e: Source Documentation. http://www.jhauser.us/arithmetic/SoftFloat-3/doc/SoftFloat-source.html.

[12]

John L. Henning. 2006. SPEC CPU2006 Benchmark Descriptions. SIGARCH Comput. Archit. News 34, 4 (Sept. 2006), 1--17.

Digital Library

[13]

Chris Lattner. 2002. LLVM: An Infrastructure for Multi-Stage Optimization. Master's thesis. Computer Science Dept., University of Illinois at Urbana-Champaign, Urbana, IL. See http://llvm.cs.uiuc.edu.

[14]

Chris Lattner and Vikram Adve. 2004. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO'04). Palo Alto, California.

Digital Library

[15]

LLVM. 2016. LLVM language reference manual. http://llvm.org/releases/3.7.1/docs/LangRef.html.

[16]

Darek Mihocka. 2010. NO EXECUTE! http://www.emulators.com/docs/nx33_qemu_0125.htm.

[17]

Andres Nötzli and Fraser Brown. 2016. LifeJacket: Verifying Precise Floating-point Optimizations in LLVM. In Proceedings of the 5th ACM SIGPLAN International Workshop on State Of the Art in Program Analysis (SOAP 2016). ACM, New York, NY, USA, 24--29.

Digital Library

[18]

QEMU. 2019. Features/Softfloat. https://wiki.qemu.org/Features/Softfloat.

[19]

Eric M. Schwarz, Martin Schmookler, and Son Dao Trong. 2003. Hardware Implementations of Denormalized Numbers. In Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03) (ARITH '03). IEEE Computer Society, Washington, DC, USA, 70--. http://dl.acm.org/citation.cfm?id=786450.786618

Digital Library

[20]

Bor-Yeh Shen, Jiunn-Yeu Chen, Wei-Chung Hsu, and Wuu Yang. 2012. LLBT: An LLVM-based Static Binary Translator. In Proceedings of the 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES '12). ACM, New York, NY, USA, 51--60.

Digital Library

[21]

Bor-Yeh Shen, Wei-Chung Hsu, and Wuu Yang. 2014. A Retargetable Static Binary Translator for the ARM Architecture. ACM Trans. Archit. Code Optim. 11, 2, Article 18 (June 2014), 25 pages.

Digital Library

[22]

Bor-Yeh Shen, Jyun-Yan You, Wuu Yang, and Wei-Chung Hsu. 2012. An LLVM-based hybrid binary translation system. In SIES. IEEE, 229--236. http://dblp.unitrier.de/db/conf/sies/sies2012.html#ShenYYH12

[23]

Richard L. Sites, Anton Chernoff, Matthew B. Kirk, Maurice P. Marks, and Scott G. Robinson. 1993. Binary Translation. Commun. ACM 36, 2 (Feb. 1993), 69--81.

Digital Library

[24]

Jim Smith and Ravi Nair. 2005. Virtual Machines: Versatile Platforms for Systems and Processes (The Morgan Kaufmann Series in Computer Architecture and Design). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.

Digital Library

Cited By

Zurstraßen NBosbach NJoseph JJünger LWeinstock JLeupers R(2023)Efficient RISC-V-on-x64 Floating Point Simulation2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00090(558-565)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00090
Rocha RSprokholt DFink MGouicem RSpink TChakraborty SBhatotia PJhala RDillig I(2022)Lasagne: a static binary translator for weak memory model architecturesProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523719(888-902)Online publication date: 9-Jun-2022
https://dl.acm.org/doi/10.1145/3519939.3523719
Huang JYang WYou Y(2022)Profile-guided optimisation for indirect branches in a binary translatorConnection Science10.1080/09540091.2022.204155534:1(749-765)Online publication date: 19-Feb-2022
https://doi.org/10.1080/09540091.2022.2041555
Show More Cited By

Index Terms

Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
  2. Software organization and properties
    1. Contextual software domains
      1. Software infrastructure
        Virtual machines
    2. Software system structures
      1. Software architectures
        Simulator / interpreter

Recommendations

Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms
ICPP Workshops '21: 50th International Conference on Parallel Processing Workshop

Rabbit is an LLVM-based hybrid binary translator with many diverse optimizations to improve the performance. In addition to platform-independent hyperchaining (indep), Rabbit also includes platform-dependent hyperchaining (dep) on both x86-64 and RISC-V ...
Hyperchaining for LLVM-Based Binary Translators on the x86-64 Platform
Abstract
Rabbit is an LLVM-based hybrid binary translator with several innovative optimizations (including an extension to traditional block chaining, called hyperchaining) to improve the performance. In addition to platform-independent hyperchaining (...
Translating the ARM Neon and VFP instructions in a binary translator

Binary translation attempts to emulate one instruction set with another on the same or different platforms. The important technique is widely used in modern software. Vector and floating-point instructions are widely used in many applications, including ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

ICPP Workshops '19: Workshop Proceedings of the 48th International Conference on Parallel Processing

August 2019

241 pages

ISBN:9781450371964

DOI:10.1145/3339186

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

University of Tsukuba: University of Tsukuba

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 August 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Funding Sources

Ministry of Science and Technology, Taiwan

Conference

ICPP 2019

ICPP 2019: Workshops

August 5 - 8, 2019

Kyoto, Japan

Acceptance Rates

Overall Acceptance Rate 91 of 313 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
201
Total Downloads

Downloads (Last 12 months)22
Downloads (Last 6 weeks)1

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Zurstraßen NBosbach NJoseph JJünger LWeinstock JLeupers R(2023)Efficient RISC-V-on-x64 Floating Point Simulation2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00090(558-565)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00090
Rocha RSprokholt DFink MGouicem RSpink TChakraborty SBhatotia PJhala RDillig I(2022)Lasagne: a static binary translator for weak memory model architecturesProceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation10.1145/3519939.3523719(888-902)Online publication date: 9-Jun-2022
https://dl.acm.org/doi/10.1145/3519939.3523719
Huang JYang WYou Y(2022)Profile-guided optimisation for indirect branches in a binary translatorConnection Science10.1080/09540091.2022.204155534:1(749-765)Online publication date: 19-Feb-2022
https://doi.org/10.1080/09540091.2022.2041555
Lai JYang W(2022)Hyperchaining for LLVM-Based Binary Translators on the x86-64 PlatformJournal of Signal Processing Systems10.1007/s11265-022-01803-194:12(1569-1589)Online publication date: 1-Dec-2022
https://dl.acm.org/doi/10.1007/s11265-022-01803-1
Lai JYang W(2021)Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms50th International Conference on Parallel Processing Workshop10.1145/3458744.3473348(1-9)Online publication date: 9-Aug-2021
https://dl.acm.org/doi/10.1145/3458744.3473348

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten