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Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II

Published: 17 October 2019 Publication History

Abstract

Verilog is a hardware description language (HDL) that supports the specification of hardware circuitry and control logic for production, simulation and testing. The subset of the specification used for production is called synthesizable. Verilog-to-Routing (VTR) is a Computer-Aided Design (CAD) flow. It transforms synthesizable Verilog into a placed and routed configuration for a Field Programmable Gate Array (FPGA) architecture specified in XML. The front end of the VTR CAD flow is Odin II. Odin II parses Verilog files and uses them to create a netlist consisting of inputs, outputs, nodes, and connections. Odin II is an open-source research project, and full Verilog language coverage is a work in progress. This work extends Odin II's Verilog support to files containing the arithmetic right shift operator (>>>) and both the + : and - : part-select operators. It also adds support for simple for loops, while loops and loop-based module generation. Dynamic looping constructs are not synthesizable, so all looping constructs are processed before the netlist is generated. This paper will present the missing language features that were implemented, the scope of their implementation, the architecture of the solution, testing and finally the efficiency of the contributions.

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cover image ACM Conferences
RSP '19: Proceedings of the 30th International Workshop on Rapid System Prototyping (RSP'19)
October 2019
80 pages
ISBN:9781450368476
DOI:10.1145/3339985
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 October 2019

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Author Tags

  1. Compiler
  2. Computer-Aided-Design
  3. FPGA
  4. Tool
  5. Verilog
  6. Verilog-to-Routing

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  • Research-article
  • Research
  • Refereed limited

Funding Sources

  • Natural Sciences and Engineering Research Council

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ESWEEK '19
ESWEEK '19: Fifteenth Embedded Systems Week
October 17 - 18, 2019
NY, New York, USA

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