short-paper

Combining error statistics with failure prediction in memory page offlining

Authors:

Cong LiAuthors Info & Claims

MEMSYS '19: Proceedings of the International Symposium on Memory Systems

Pages 127 - 132

https://doi.org/10.1145/3357526.3357527

Published: 30 September 2019 Publication History

Abstract

Memory errors constitute a large fraction of total hardware failures on modern systems, negatively impacting their reliability, availability, and serviceability. Error correcting codes have been developed to detect and correct the errors. Error-prevention mechanisms such as soft page offlining has been implemented in modern operating systems. Common offlining policies are based on error rate statistics in a certain past period. However, future error occurrences depend on both the wear level of the faulty memory cells and the implicit runtime context which may not be reflected in the statistics in the period. This paper proposes a new offlining policy which combines error statistics with failure prediction of the memory cells in a page. Using a failure prediction component, the new approach is more effective in mining the combined effect of both the hardware wear level and the runtime context. Scoring with both the error statistics and the prediction confidence, the new policy is more comprehensive in offlining error-prone pages to avoid more errors. Empirical evaluation demonstrates that the new policy outperforms the baseline policies based on historical error statistics.

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Cited By

Wu RZhou SLu JShen ZXu ZShu JYang KLin FZhang YBagchi SZhang Y(2024)Removing obstacles before breaking through the memory wallProceedings of the 2024 USENIX Conference on Usenix Annual Technical Conference10.5555/3691992.3692044(851-867)Online publication date: 10-Jul-2024
https://dl.acm.org/doi/10.5555/3691992.3692044
Yu QZhang WZhou MYu JSheng ZBogatinovski JCardoso JKao O(2024)Investigating Memory Failure Prediction Across CPU Architectures2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)10.1109/DSN-S60304.2024.00033(88-95)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN-S60304.2024.00033
Jung JErez M(2023)Predicting Future-System Reliability with a Component-Level DRAM Fault ModelProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614294(944-956)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614294
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Index Terms

Combining error statistics with failure prediction in memory page offlining
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Hardware
  1. Robustness
    1. Fault tolerance
      1. Failure prediction

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cover image ACM Other conferences

MEMSYS '19: Proceedings of the International Symposium on Memory Systems

September 2019

517 pages

ISBN:9781450372060

DOI:10.1145/3357526

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 September 2019

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MEMSYS '19

MEMSYS '19: The International Symposium on Memory Systems

September 30 - October 3, 2019

District of Columbia, Washington, USA

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Cited By

Wu RZhou SLu JShen ZXu ZShu JYang KLin FZhang YBagchi SZhang Y(2024)Removing obstacles before breaking through the memory wallProceedings of the 2024 USENIX Conference on Usenix Annual Technical Conference10.5555/3691992.3692044(851-867)Online publication date: 10-Jul-2024
https://dl.acm.org/doi/10.5555/3691992.3692044
Yu QZhang WZhou MYu JSheng ZBogatinovski JCardoso JKao O(2024)Investigating Memory Failure Prediction Across CPU Architectures2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)10.1109/DSN-S60304.2024.00033(88-95)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN-S60304.2024.00033
Jung JErez M(2023)Predicting Future-System Reliability with a Component-Level DRAM Fault ModelProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614294(944-956)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614294
Yu QZhang WCardoso JKao O(2023)Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323692(01-09)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323692
Yu QZhang WNotaro PHaeri SCardoso JKao O(2023)HiMFP: Hierarchical Intelligent Memory Failure Prediction for Cloud Service Reliability2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58367.2023.00031(216-228)Online publication date: Jun-2023
https://doi.org/10.1109/DSN58367.2023.00031
Lee JKim MKim WKim Y(2023)Review of Memory RAS for Data CentersIEEE Access10.1109/ACCESS.2023.332998411(124782-124796)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3329984
Li CZhang YWang JChen HLiu XHuang TPeng LZhou SWang LGe SWolf FShende SCulhane CAlam SJagode H(2022)From correctable memory errors to uncorrectable memory errorsProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.5555/3571885.3571986(1-14)Online publication date: 13-Nov-2022
https://dl.acm.org/doi/10.5555/3571885.3571986
Li CZhang YWang JChen HLiu XHuang TPeng LZhou SWang LGe S(2022)From Correctable Memory Errors to Uncorrectable Memory Errors: What Error Bits TellSC22: International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC41404.2022.00081(01-14)Online publication date: Nov-2022
https://doi.org/10.1109/SC41404.2022.00081
Zhang PWang YMa XXu YYao BZheng XJiang L(2022)Predicting DRAM-Caused Node Unavailability in Hyper-Scale Clouds2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN53405.2022.00037(275-286)Online publication date: Jun-2022
https://doi.org/10.1109/DSN53405.2022.00037
Du XLi C(2021)Predicting Uncorrectable Memory Errors from the Correctable Error History: No Free Predictors in the FieldProceedings of the International Symposium on Memory Systems10.1145/3488423.3519316(1-10)Online publication date: 27-Sep-2021
https://dl.acm.org/doi/10.1145/3488423.3519316
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