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Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing

Published: 17 October 2019 Publication History

Abstract

It is known that one-sided net untangling can be used to untangle the twisted nets inside a bus for single-layer bus routing. However, limited space behind one pin-row may make one-sided net untangling unsuccessful for single-layer bus routing. In this article, the concept of using internal detours on untangled nets can be introduced into two-sided net untangling. Given a set of 2-pin nets inside a bus, based on two one-sided untangling results with internal detours on untangled nets [8], an efficient algorithm first uses a minimal set of internal detours to guarantee that the crossing conditions of the given nets inside the bus can be eliminated in one initial two-sided untangling result with no capacity constraint behind two pin-rows and between two adjacent pins inside any pin-row. Furthermore, based on the maintenance of the non-crossing constraint on any pair of nets and the capacity constraint behind two pin-rows in one initial two-sided untangling result, an iterative rip-up-and-reassign algorithm can be proposed to eliminate the possible capacity violations between two adjacent pins inside two pin-rows to route a maximal set of nets in two-sided net untangling. Compared with Yan's one-sided net untangling [8] for 12 tested examples with different capacity constraints, the experimental results show that our proposed two-sided untangling algorithm can improve 3.5% of routability and use the benefit of more routing space behind two pin-rows to reduce 86.4% of the used internal detours on average in reasonable CPU time. Compared with Yan's two-sided net untangling [9] for 12 tested examples with different capacity constraints, the experimental results show that our proposed two-sided untangling algorithm can improve 2.8% of routability by introducing some internal detours and using iterative rip-up-and-reassign on the average in reasonable CPU time.

References

[1]
M. M. Ozdal and M. D. F. Wong. 2006. Algorithmic study of single-layer bus routing for high-speed boards. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 25, 3 (2006), 490--503.
[2]
M. M. Ozdal and M. D. F. Wong. 2006. A length-matching routing algorithm for high-performance printed circuit boards. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 25, 12 (2006), 2784--2794.
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T. Yan and M. D. F. Wong. 2008. BSG-Route: A length-matching router for general topology. In Proceedings of the IEEE International Conference on Computer-Aided Design. 499--505.
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J. T. Yan and Z. W. Chen. 2011. Obstacle-aware length-matching bus routing. In Proceedings of the International Symposium on Physical Design. 61--67.
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R. Y. Pinter. 1983. River routing: Methodology and analysis. In Proceedings of the 3rd Caltech Conference on Very Large Scale Integration. 141--163.
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T. Yan and D. F. Wong. 2007. Untangling twisted nets for bus routing. In Proceedings of the IEEE International Conference on Computer-Aided Design. 396--400.
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T. Lin, S. Dong, S. Chen, and S. Goto. Linear optimal one-sided single-detour algorithm for untangling twisted bus. In Proceedings of the Asia-South-Pacific Design Automation Conference. 151--156.
[8]
J. T. Yan. 2017. One-sided net untangling with internal detours for bus routing. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 36, 6 (2017), 952--963.
[9]
J. T. Yan and Z. W. Chen. 2010. Two-sided single-detour untangling for bus routing. In Proceedings of the Design Automation Conference. 206--211.
[10]
J. T. Yan. 2000. Hierarchical bubble-sorting-based non-Manhattan channel routing. IEEE Proc.-E: Comput. Dig. Tech. 147, 4 (2000), 215--220.
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  1. Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 24, Issue 6
    November 2019
    275 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3357467
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 17 October 2019
    Accepted: 01 August 2019
    Revised: 01 May 2019
    Received: 01 April 2018
    Published in TODAES Volume 24, Issue 6

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    Author Tags

    1. PCB design
    2. bus routing
    3. net untangling
    4. single-layer routing

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