research-article

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

Authors:

Rongjian Liang,

Jiang HuAuthors Info & Claims

ISPD '20: Proceedings of the 2020 International Symposium on Physical Design

Pages 135 - 142

https://doi.org/10.1145/3372780.3375560

Published: 30 March 2020 Publication History

Abstract

As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.

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Cited By

Almeida SNetto RFontana TAghaeekiasaraee EGandhi UTabrizi AGüntzel JBehjat LMeinhardt C(2025)Eh-DRVPIntegration, the VLSI Journal10.1016/j.vlsi.2024.102309101:COnline publication date: 1-Mar-2025
https://dl.acm.org/doi/10.1016/j.vlsi.2024.102309
Hyun DJung YShin Y(2024)Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336451932:5(823-834)Online publication date: May-2024
https://doi.org/10.1109/TVLSI.2024.3364519
Li SZhu SLiu LZeng ZChang SWang HWu HGuo TWu CLiu C(2024)Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric ThicknessIEEE Transactions on Electron Devices10.1109/TED.2023.334367871:2(1089-1096)Online publication date: Feb-2024
https://doi.org/10.1109/TED.2023.3343678
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Index Terms

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
2. Theory of computation
  1. Theory and algorithms for application domains

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Published In

cover image ACM Conferences

ISPD '20: Proceedings of the 2020 International Symposium on Physical Design

March 2020

160 pages

ISBN:9781450370912

DOI:10.1145/3372780

General Chair:
William Swartz
TimberWolf Systems and University of Texas at Dallas, USA
,
Program Chair:
Jens Lienig
Dresden University of Technology, Germany

Copyright © 2020 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 March 2020

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Semiconductor Research Corporation

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ISPD '20: International Symposium on Physical Design

September 20 - 23, 2020

Taipei, Taiwan

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Almeida SNetto RFontana TAghaeekiasaraee EGandhi UTabrizi AGüntzel JBehjat LMeinhardt C(2025)Eh-DRVPIntegration, the VLSI Journal10.1016/j.vlsi.2024.102309101:COnline publication date: 1-Mar-2025
https://dl.acm.org/doi/10.1016/j.vlsi.2024.102309
Hyun DJung YShin Y(2024)Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336451932:5(823-834)Online publication date: May-2024
https://doi.org/10.1109/TVLSI.2024.3364519
Li SZhu SLiu LZeng ZChang SWang HWu HGuo TWu CLiu C(2024)Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric ThicknessIEEE Transactions on Electron Devices10.1109/TED.2023.334367871:2(1089-1096)Online publication date: Feb-2024
https://doi.org/10.1109/TED.2023.3343678
Park HBaek KKim SChoi KKim T(2024)Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and SustainabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340589443:12(4786-4799)Online publication date: Dec-2024
https://doi.org/10.1109/TCAD.2024.3405894
Chang CPan JXie ZZhang THu JChen Y(2024)Toward Fully Automated Machine Learning for Routability Estimator DevelopmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333081843:3(970-982)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3330818
Peneda DAzevedo FLourenço NHorta NMartins R(2024)Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745385(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745385
Wu HZuo X(2024)GOA Panel Routability Improvement Algorithm Based on Flexible via Layout2024 5th International Symposium on Computer Engineering and Intelligent Communications (ISCEIC)10.1109/ISCEIC63613.2024.10810152(210-216)Online publication date: 8-Nov-2024
https://doi.org/10.1109/ISCEIC63613.2024.10810152
Zhang XTian HWang CJi WKou MYao H(2024)DRV Prediction Using Quantum-Classical Hybrid Convolutional Neural Network2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814139(333-338)Online publication date: 25-Oct-2024
https://doi.org/10.1109/ICICM63644.2024.10814139
Chen YZhang DChen H(2024)A Standard Deviation Incorporated Attention Module Enhanced U-Net for Routability Prediction2024 9th International Conference on Electronic Technology and Information Science (ICETIS)10.1109/ICETIS61828.2024.10593700(671-674)Online publication date: 17-May-2024
https://doi.org/10.1109/ICETIS61828.2024.10593700
Liu QLing MZhu YRui YWang R(2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
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