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DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

Published: 30 March 2020 Publication History

Abstract

As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.

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  1. DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

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        cover image ACM Conferences
        ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
        March 2020
        160 pages
        ISBN:9781450370912
        DOI:10.1145/3372780
        • General Chair:
        • William Swartz,
        • Program Chair:
        • Jens Lienig
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Publication History

        Published: 30 March 2020

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        Author Tags

        1. convolutional network
        2. drc prediction
        3. machine learning
        4. sub-10nm process node

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        ISPD '20
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        ISPD '20: International Symposium on Physical Design
        September 20 - 23, 2020
        Taipei, Taiwan

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        Overall Acceptance Rate 62 of 172 submissions, 36%

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        Cited By

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        • (2024)Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336451932:5(823-834)Online publication date: May-2024
        • (2024)Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric ThicknessIEEE Transactions on Electron Devices10.1109/TED.2023.334367871:2(1089-1096)Online publication date: Feb-2024
        • (2024)Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and SustainabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340589443:12(4786-4799)Online publication date: Dec-2024
        • (2024)Toward Fully Automated Machine Learning for Routability Estimator DevelopmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333081843:3(970-982)Online publication date: Mar-2024
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        • (2024)DRV Prediction Using Quantum-Classical Hybrid Convolutional Neural Network2024 9th International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICICM63644.2024.10814139(333-338)Online publication date: 25-Oct-2024
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        • (2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
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