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Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV

Published: 30 March 2020 Publication History

Abstract

On-Chip Variation (OCV) in advanced technology nodes introduces delay uncertainties that may cause timing violations. This problem drastically affects the clock tree that, besides the growing design complexity, needs to be appropriately synthesized to tackle the increased variability effects. To reduce the magnitude of the clock-induced OCV, we incrementally relocate the flip-flops and the clock gaters in a bottom-up manner to implicitly guide the clock tree synthesis engine to produce clock trees with increased common clock tree paths. The relocation of the clock elements is performed using a soft clustering approach that is orthogonal to the clock tree synthesis method used. The clock elements are repeatedly relocated and incrementally re-clustered, thus gradually forming better clusters and settling to more appropriate positions to increase the common paths of the clock tree. This behavior is verified by applying the proposed method in industrial designs, resulting in clock trees which are more resilient to process variations, while exhibiting improved overall timing.

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  1. Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV

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        cover image ACM Conferences
        ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
        March 2020
        160 pages
        ISBN:9781450370912
        DOI:10.1145/3372780
        • General Chair:
        • William Swartz,
        • Program Chair:
        • Jens Lienig
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        Published: 30 March 2020

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        Author Tags

        1. clock tree synthesis
        2. flip-flop placement
        3. on-chip variations
        4. soft clustering

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        ISPD '20: International Symposium on Physical Design
        September 20 - 23, 2020
        Taipei, Taiwan

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