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Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation

Published: 30 March 2020 Publication History

Abstract

Design optimization modifies a netlist with the goal of satisfying the timing constraints at the minimum area and leakage power, without violating any slew or load capacitance constraints. Lagrangian relaxation (LR) based optimization has been established as a viable approach for this. We extend LR-based optimization by interleaving in each iteration techniques such as: gate and flip-flop sizing; buffering to fix late and early timing violations; pin swapping; and useful clock skew. Locally optimal decisions are made using LR-based cost functions, without the need for incremental timing updates. Sub-steps are applied in a balanced manner, accounting for the expected savings and any conflicting timing violations, maximizing the final quality of results under multiple process/operating corners with a reasonable runtime. Experimental results show that our approach achieves better timing, and both lower area and leakage power than the winner of the TAU 2019 contest, on those benchmarks.

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Cited By

View all
  • (2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: Apr-2023
  • (2021)Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302554140:8(1672-1686)Online publication date: Aug-2021
  • (2021)Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST52088.2021.9493338(1-5)Online publication date: 5-Jul-2021

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  1. Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation

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    cover image ACM Conferences
    ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
    March 2020
    160 pages
    ISBN:9781450370912
    DOI:10.1145/3372780
    • General Chair:
    • William Swartz,
    • Program Chair:
    • Jens Lienig
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 30 March 2020

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    Author Tags

    1. buffering
    2. lagrangian relaxation
    3. optimization
    4. sizing
    5. useful skew

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    ISPD '20: International Symposium on Physical Design
    September 20 - 23, 2020
    Taipei, Taiwan

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    Overall Acceptance Rate 62 of 172 submissions, 36%

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    Cited By

    View all
    • (2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: Apr-2023
    • (2021)Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302554140:8(1672-1686)Online publication date: Aug-2021
    • (2021)Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST52088.2021.9493338(1-5)Online publication date: 5-Jul-2021

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