Welcome to LCTES 2020, the 21th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems. This year's LCTES conference is co-located with PLDI 2020.
LCTES continues to provide a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems, but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact.
This year's LCTES program consists of one keynote presentation on "Compiler 2.0: Using Machine Learning to Modernize Compiler Technology" by Prof. Saman Amarasinghe, MIT, eleven full paper presentations, and five work-in-progress (WIP) paper presentations.
LCTES 2020 followed a double-blind submission process for all the paper reviews. Each paper received at least four reviews. Reviews were submitted over the HotCRP system. A one-week online PC meeting was held, in which every paper was thoroughly discussed, and acceptance decisions were made based on overall merit ratings. This year, a total of 10 WIP papers and 39 full papers were submitted and reviewed. The program committee selected 5 WIP papers and 11 full papers for acceptance. This represents an acceptance rate of 28% for full papers (50% for WIP papers).
Proceeding Downloads
Compiler 2.0: Using Machine Learning to Modernize Compiler Technology
Modern compilers are still built using technology that existed decades ago. These include basic algorithms and techniques for lexing, parsing, data-flow analysis, data dependence analysis, vectorization, register allocation, instruction selection, and ...
PAQSIM: Fast Performance Model for Graphics Workload on Mobile GPUs
As the popularity of GPU in embedded systems keeps increasing, there is a growing demand for performance models for rapid estimation and tuning. One major challenge of developing a GPU performance model is the balance between accuracy and speed. The ...
A Collaborative Filtering Approach for the Automatic Tuning of Compiler Optimisations
Selecting the right compiler optimisations has a severe impact on programs' performance. Still, the available optimisations keep increasing, and their effect depends on the specific program, making the task human intractable. Researchers proposed ...
ApproxRefresh: Enabling Uncorrectable Data Reuse on Flash Memory with Approximate Read Awareness
With the increased density and the technology scaling, flash memory is more vulnerable to noise effects, overwhelmingly lowering the data retention time. The periodic data refresh technique is commonly used to retain the long-term data integrity. ...
Compiling Spiking Neural Networks to Neuromorphic Hardware
Machine learning applications that are implemented with spike-based computation model, e.g., Spiking Neural Network (SNN), have a great potential to lower the energy consumption when executed on a neuromorphic hardware. How- ever, compiling and mapping ...
Performance Optimization on big.LITTLE Architectures: A Memory-latency Aware Approach
The energy demands of modern mobile devices have driven a trend towards heterogeneous multi-core systems which include various types of core tuned for performance or energy efficiency, offering a rich optimization space for software. On such systems, ...
Path Sensitive Signatures for Control Flow Error Detection
Transistors' performance has been improving by shrinking feature sizes, lowering voltage levels, and reducing noise margins. However, these changes also make transistors more vulnerable and susceptible to transient faults. As a result, transient fault ...
Exploiting the Trust Between Boundaries: Discovering Memory Corruptions in Printers via Driver-Assisted Testing
- Xiaoyu He,
- Erick Bauman,
- Feng Li,
- Lei Yu,
- Linyu Li,
- Bingchang Liu,
- Aihua Piao,
- Kevin W. Hamlen,
- Wei Huo,
- Wei Zou
TrustScope is a new, a practical approach to identifying vulnerabilities in printer firmware without actually touching the firmware. By exploiting the trust between the firmware and the device drivers, TrustScope analyzes driver software to identify the ...
Intermittent Computing with Peripherals, Formally Verified
Transiently-powered systems featuring non-volatile memory as well as external peripherals enable the development of new low-power sensor applications. However, as programmers, we are ill-equipped to reason about systems where power failures are the norm ...
CITTA: Cache Interference-aware Task Partitioning for Real-time Multi-core Systems
Shared caches in multi-core processors introduce serious difficulties in providing guarantees on the real-time properties of embedded software due to the interaction and the resulting contention in the shared caches. Prior work has studied the ...
A Synergistic Approach to Predictable Compilation and Scheduling on Commodity Multi-Cores
Commodity multi-cores are still uncommon in real-time systems, as resource sharing complicates traditional timing analysis. The Predictable Execution Model (PREM) tackles this issue in software, through scheduling and code refactoring. State-of-the-art ...
Improving the Performance of WCET Analysis in the Presence of Variable Latencies
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time (wcet) analysis methods tend to scale poorly to modern hardware architectures. As a result, a tradeoff must be made between ...
A Synthesis-Aided Compiler for DSP Architectures (WiP Paper)
Digital signal processors (DSPs) offer cutting-edge energy efficiency for embedded multimedia computations, but writing high-performance DSP code requires expert tuning. Programmers need to work at a low level of abstraction, manually tailoring vendor-...
Towards Real-time CNN Inference from a Video Stream on a Mobile GPU (WiP Paper)
While there are several frameworks for CNN inference on mobile GPUs, they do not achieve real-time processing for the most of the CNNs that aim at reasonable accuracy since they all employ kernel-by-kernel execution model and do not effectively support ...
Beyond Base-2 Logarithmic Number Systems (WiP Paper)
Logarithmic number systems (LNS) reduce hardware complexity for multiplication and division in embedded systems, at the cost of more complicated addition and subtraction. Existing LNS typically use base-2, meaning that representable numbers are some (...
Towards Building Better Mobile Web Browsers for Ad Blocking: The Energy Perspective (WiP Paper)
Advertisements, or ads, are a major source of income for Internet-related service companies. Meanwhile, ads and trackers consume significant computing resources and power, which are crucial for mobile devices, and can drain a phone's battery. Moreover, ...
FPGA-based Near Data Processing Platform Selection Using Fast Performance Modeling (WiP Paper)
With the trend of adopting FPGAs in data centers, various FPGA acceleration platforms have been developed in recent years. Each server could incorporate one or many of these FPGAs at different compute hierarchy levels to match its workload intensity. ...
- The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems