On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing

Routing is one of the most time-consuming steps in the FPGA synthesis flow. Existing works have described several ways to accelerate the routing process. The partitioning-based parallel routing technique that leverages the high-performance computing of multi-core processors are gaining popularity recently. Specifically, those parallel routers partition nets to regions by nets' bounding boxes, followed by a parallel routing procedure. Nets can be split up into source-sink connections that share wire segments as much as possible. In order to exploit more parallelism by a finer granularity in both spatial partitioning and routing, a connection-aware routing bounding box model is introduced in this work. We first explore in detail to show that connection-aware partitioning using the new routing bounding boxes enables the parallel routing to perform better runtime efficiency than the existing net-based partitioning by analyzing the workloads of parallel routers. It reduces the connections spanning more than one region and exploits more parallelism. The large heterogeneous Titan23 designs and a detailed representation of the Stratix IV FPGA are used for benchmarking. Experimental results show that the parallel FPGA router is faster when using our connection-aware partitioning than using the existing net-based partitioning, while achieving similar quality of routing results in terms of the wirelength and critical path delay. The connection-aware routing bounding box model is easy to be embedded into other existing parallel routers and further enables them to be faster.