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CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing

Published: 16 November 2020 Publication History

Abstract

A novel simulation-based framework that applies classification with adaptive labeling thresholds (CALT) is developed that auto-generates the component sizes of an analog integrated circuit. Classifiers are applied to predict whether the target specifications are satisfied. To address the lack of data points with positive labels due to the large dimensionality of the parameter space, the labeling threshold is adaptively set to a certain percentile of the distribution of a given circuit performance metric in the dataset. Random forest classifiers are executed for surrogate prediction modeling that provide a ranking of the design parameters. For each iteration of the simulation loop, optimization is utilized to determine new query points. CALT is applied to the design of a low noise amplifier (LNA) in a 65 nm technology. Qualified design solutions are generated for two sets of specifications with an average execution of 4 and 17 iterations of the optimization loop, which require an average of 1287 and 2190 simulation samples, and an average execution time of 5.4 hours and 23.2 hours, respectively. CALT is a specification-driven design framework to automate the sizing of the components (transistors, capacitors, inductors, etc.) of an analog circuit. CALT generates interpretable models and achieves high sample efficiency without requiring the use of prior circuit models.

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Cited By

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  • (2023)Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181617(1-5)Online publication date: 21-May-2023
  • (2022)Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural NetworksProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3551901.3556488(159-165)Online publication date: 12-Sep-2022
  • (2022)Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD55463.2022.9900087(159-165)Online publication date: 12-Sep-2022
  • Show More Cited By

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cover image ACM Conferences
MLCAD '20: Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD
November 2020
183 pages
ISBN:9781450375191
DOI:10.1145/3380446
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 November 2020

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Author Tags

  1. analog EDA
  2. analog circuit optimization
  3. analog circuit sizing
  4. classification
  5. machine learning for analog design

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MLCAD '20
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MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD
November 16 - 20, 2020
Virtual Event, Iceland

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Cited By

View all
  • (2023)Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181617(1-5)Online publication date: 21-May-2023
  • (2022)Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural NetworksProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3551901.3556488(159-165)Online publication date: 12-Sep-2022
  • (2022)Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD55463.2022.9900087(159-165)Online publication date: 12-Sep-2022
  • (2022)Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937457(1033-1037)Online publication date: 28-May-2022
  • (2021)Variation-aware Analog Circuit Sizing with Classifier Chains2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD52597.2021.9531273(1-6)Online publication date: 30-Aug-2021

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