Accelerating Chip Design with Machine Learning

As Moore's law has provided an exponential increase in chip transistor density, the unique features we can now include in large chips are no longer predominantly limited by area constraints. Instead, new capabilities are increasingly limited by the engineering effort associated with digital design, verification, and implementation. As applications demand more performance and energy efficiency from specialization in the post-Moore's-law era, we expect required complexity and design effort to increase.

Historically, these challenges have been met through levels of abstraction and automation. Over the last few decades, Electronic Design Automation (EDA) algorithms and methodologies were developed for all aspects of chip design - design verification and simulation, logic synthesis, place-and-route, and timing and physical signoff analysis. With each increase in automation, total work per chip has increased, but more work has also been offloaded from manual effort to software. Just as machine learning (ML) has transformed software in many domains, we expect advancements in ML will also transform EDA software and as a result, chip design workflows.

In this talk, we highlight work from our research group and the community applying ML to various chip design prediction tasks [1]. We show how deep convolutional neural networks [2] and graph-based neural networks [3] can be used in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted chip design workflow to automate optimization tasks. In this future vision, GPU acceleration, neural-network predictors, and deep reinforcement learning techniques combine to automate VLSI design and optimization.