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Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization

Published: 22 May 2020 Publication History

Abstract

Traditional memory technologies face severe challenges in meeting the ever-increasing power and memory bandwidth requirements for high-performance computing and big-data analyses. Several emerging memory technologies are promising as the replacements of SRAM or DRAM. Among them, STT-MRAM can be used to replace SRAM as the last-level cache (LLC). However, it suffers from high write energy and latency. In this article, we investigate data patterns written from SRAM-based upper-level cache to STT-MRAM-based LLC to explore the write energy reduction potential. Depending on the data layout within a cache line, redundant bits can be identified and eliminated from write back operations to save STT-MRAM write energy. We also propose a dynamic profiling method to accommodate different application characteristics. The extensive simulation results show that write energy can be saved by 37.05% ∼ 38.89% for static profiling and 19.76% ∼ 34.29% for dynamic profiling.

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  • (2024)Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systemsSemiconductor Science and Technology10.1088/1361-6641/ad504339:9(095003)Online publication date: 1-Aug-2024
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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 16, Issue 3
    Special Issue on Nanoelectronic Device, Circuit, and Architecture Design, Part 1 and Regular Papers
    July 2020
    214 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/3399633
    • Editor:
    • Ramesh Karri
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 22 May 2020
    Online AM: 07 May 2020
    Accepted: 01 February 2020
    Revised: 01 November 2019
    Received: 01 May 2019
    Published in JETC Volume 16, Issue 3

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    Author Tags

    1. STT-MRAM
    2. cache hierarchy
    3. data patterns
    4. write energy reductions

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    • Science, Technology and Innovation Commission of Shenzhen Municipality
    • Beijing Natural Science Foundation

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    View all
    • (2024)Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systemsSemiconductor Science and Technology10.1088/1361-6641/ad504339:9(095003)Online publication date: 1-Aug-2024
    • (2024)Advanced hybrid MRAM based novel GPU cache system for graphic processing with high efficiencyAIP Advances10.1063/9.000072114:1Online publication date: 25-Jan-2024
    • (2023)MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUsIEEE Transactions on Magnetics10.1109/TMAG.2023.326746759:6(1-14)Online publication date: Jun-2023
    • (2023)Hierarchical cache configuration based on hybrid SOT- and STT-MRAMAIP Advances10.1063/9.000041513:2Online publication date: 3-Feb-2023
    • (2022)Elastic adaptive prefetching for non-volatile cache in IoT terminalsIEICE Electronics Express10.1587/elex.19.2022022519:13(20220225-20220225)Online publication date: 10-Jul-2022

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