Protection of Memory Using Code Redundancies: A Brief Study
Article No.: 53, Pages 1 - 6
Abstract
Experimental results have shown that the Neutron and proton induced upset is the root cause of increasing the sensitivity of microelectronics to soft errors. Thus eliminating these errors are the main challenge to overcome while designing and implementing any microelectronic device, error detection and correction technologies are practical ways that could be applied to fulfill such a purpose. Hamming code, Reed-Solomon codes, Parity Matrix codes, and many more techniques, have been developed and used over the last decades targeting memory protection. Which are still delivering qualified performance measures; however, the downside of these approaches is that they necessitate more redundant memory space, transmission delay, and sophisticated reliability architecture. This paper highlights various memory protection technologies, particularly emphasizing on The Decimal matrix code (DMC) with Encoder Reuse Technique (ERT).
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- Protection of Memory Using Code Redundancies: A Brief Study
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Published In
September 2019
397 pages
ISBN:9781450376617
DOI:10.1145/3386164
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Published: 06 June 2020
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ISCSIC 2019
ISCSIC 2019: 2019 3rd International Symposium on Computer Science and Intelligent Control
September 25 - 27, 2019
Amsterdam, Netherlands
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ISCSIC 2019 Paper Acceptance Rate 77 of 152 submissions, 51%;
Overall Acceptance Rate 192 of 401 submissions, 48%
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