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Hardware Scheduler Implementation based on Replicated Resource Architecture for Reconfigurable Systems

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Published:06 June 2020Publication History

ABSTRACT

Among many others aspects, technological improvements in the field of microelectronics and microprocessor architectures have radically changed modern systems integrated in real-time applications. The purpose of this study is to extend the hardware implementation of real-time operating system functions (HW- RTOS), thus improving the performance of the interrupt system and the hardware-handling block for events. The research presented in this paper regards the hardware implementation of the event selection mechanism and the introduction of specialized instruction to allow the automatic management of the events.

References

  1. Ayers, G. eXtensible Utah Multicore (XUM) project at the University of Utah. 2011--2012, [Online], Available: http://opencores.org/project, mips32r1, (Accessed: Sept. 2017).Google ScholarGoogle Scholar
  2. Ciobanu, E. E. The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGA. Advances in Electrical and Computer Engineering, vol.18, no.1, pp.137--144, 2018, doi: 10.4316/AECE.2018.01017.Google ScholarGoogle ScholarCross RefCross Ref
  3. Găitan, V.G., Găitan, N.C., Ungurean, I. CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1661--1674, Sept. 2015. doi:10.1109/TVLSI.2014.2346542.Google ScholarGoogle ScholarCross RefCross Ref
  4. Han, Y., Virupakshappa, K., Vitor Silva Pinto, E., Oruklu, E. Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs. MDPI Electronics 2015, 4, pp. 1062--1089. doi: 10.3390/electronics4041062.Google ScholarGoogle Scholar
  5. Koulamas, C., Lazarescu, M.T. Real-time embedded systems: Present and future. MDPI Electronics. 2018, 7, 205, doi: 10.3390/electronics7090205.Google ScholarGoogle ScholarCross RefCross Ref
  6. Lee, J., Mooney, V.J., Daleby, A., Ingstrom, K., Klevin, T., Lindh, L. A comparison of the RTU hardware RTOS with a hardware/software RTOS. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, 24 January 2003; pp. 683--688. doi: 10.1109/ASPDAC.2003.1195108.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Maruyama, N., T. Ishihara & H. Yasuura, An RTOS in hardware for energy efficient software-based TCP/IP processing, 2010 IEEE 8th Symposium on Application Specific Processors (SASP), 2010, pp. 58--63. doi: 10.1109/SASP.2010.5521147.Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Melnyk, A., Melnyk, V. Self-Configurable FPGA-Based Computer Systems. Advances in Electrical and Computer Engineering, vol.13, no.2, pp.33--38, 2013, doi:10.4316/AECE.2013.02005.Google ScholarGoogle ScholarCross RefCross Ref
  9. Moisuc, E. E., Larionescu, A.B., Găitan, V.G. Hardware Event Treating in nMPRA. In 12rt International Conference on Development and Application Systems, Suceava, Romania, pp. 66--69, May, 2014. doi: 10.1109/DAAS.2014.6842429.Google ScholarGoogle Scholar
  10. Roman, S., Mecha, H., Mozos, D. and Septien, J. Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays. In IET Computers & Digital Techniques, vol. 2, no. 6, pp. 401--412, November 2008. doi: 10.1049/iet-cdt:20070060.Google ScholarGoogle ScholarCross RefCross Ref
  11. Tucci, P. Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems, Online: https://sourceforge.net/p/xrt/, 2012.Google ScholarGoogle Scholar
  12. Vakili, S., Langlois, J. M. P. and Bois, G. Customised soft processor design: a compromise between architecture description languages and parameterisable processors. In IET Computers & Digital Techniques, vol. 7, no. 3, pp. 122--131, May 2013. doi: 10.1049/iet-cdt.2012.0088.Google ScholarGoogle ScholarCross RefCross Ref
  13. Xilinx. (2016), VC707 Evaluation Board for the Virtex-7 FPGA User Guide, [Online], Available: https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf, (Accessed: Aug. 2016).Google ScholarGoogle Scholar
  14. Zagan, I. Improving the performance of CPU architectures by reducing the Operating System overhead. In 3rd IEEE Workshop on Advances in Information, Electronic and Electrical Engineering AIEEE'2015, pp. 1--6, Nov. 2015, Riga, Latvia. doi: 10.1109/AIEEE.2015.7367279.Google ScholarGoogle ScholarCross RefCross Ref
  15. Zagan, I., Găitan, V.G. Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture. Electronics 2019, 8, 211. doi:10.3390/electronics8020211.Google ScholarGoogle Scholar

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  1. Hardware Scheduler Implementation based on Replicated Resource Architecture for Reconfigurable Systems

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      cover image ACM Other conferences
      ISCSIC 2019: Proceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control
      September 2019
      397 pages
      ISBN:9781450376617
      DOI:10.1145/3386164

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      • Published: 6 June 2020

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      ISCSIC 2019 Paper Acceptance Rate77of152submissions,51%Overall Acceptance Rate192of401submissions,48%
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