Chirag Joshi
ABSTRACT
The continuous rise of on-chip components like cores and caches has brought enormous computing capabilities at the cost of high leakage power and temperature. A recent study has shown a substantial spatial temperature variance in modern large on-chip caches. This high temperature elevates the cooling cost and becomes responsible for the thermal breakdown of the chip. One solution to reduce the leakage is the use of non-volatile memory (NVM) like STT-RAM. Other includes incorporating the concept of dark silicon. In this paper, we amalgamate the idea of using STT-RAM in the last level cache (LLC) and the dark silicon approach to shut down certain cache ways to leverage the benefits from both. We address the downsides like higher access latencies of STT-RAM by the use of hybrid cache (SRAM + STT-RAM) and weak endurance of the STT-RAM by wear leveling. We propose a system to handle three different temperature thresholds (high, medium, and low) by appropriately selecting the type of cache ways to be powered off. The proposed system delivers up to 5.38 K reduction in temperature compared to the baseline, 93% reduction in leakage power with an EDP gain up to 92%.
Supplemental Material
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Index Terms
- Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors
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