skip to main content
10.1145/3386263.3407596acmotherconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
research-article

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems

Published: 07 September 2020 Publication History

Abstract

There is growing interest in deploying energy harvesting processors and accelerators in Internet of Things (IoT). Energy harvesting harnesses the energy scavenged from the environment to power a system. Although it has many advantages over battery-operated systems such as lightweight, compact size, and no necessity of recharging and maintenance, it may suffer frequently power-down and a fluctuating power supply even with power on. Non-volatile processor (NVP) is a promising architecture for effective computing in energy harvesting scenarios. Recently, non-volatile accelerators (NVA) have been proposed to perform computations of deep learning algorithms. In this paper, we overview the recent studies of NVP and NVA across the layers of hardware, architecture, software and their co-design. Especially, we present the design insights of how the state-of-the-art works adapt their specific designs to the intermittent and fluctuating power conditions with the energy harvesting technology. Finally, we discuss recent trends using NVP and NVA in energy harvesting scenarios.

Supplementary Material

MP4 File (3386263.3407596.mp4)
There is growing interest in deploying energy harvesting processors and accelerators in Internet of Things (IoT). Energy harvesting harnesses the energy scavenged from the environment to power a system. Although it has many advantages over battery-operated systems such as lightweight, compact size, and no necessity of recharging and maintenance, it may suffer frequently power-down and a fluctuating power supply even with power on. Non-volatile processor (NVP) is a promising architecture for effective computing in energy harvesting scenarios. Recently, non-volatile accelerators (NVA) have been proposed to perform computations of deep learning algorithms. In this paper, we overview the recent studies of NVP and NVA across the layers of hardware, architecture, software and their co-design. Especially, we present the design insights of how the state-of-the-art works adapt their specific designs to the intermittent and fluctuating power conditions with the energy harvesting technology.

References

[1]
https://www.ubuntupit.com/top-20-emerging-iot-trends-that-will-shape-your-future-soon/.
[2]
A. S. H. Mayue Shi, Eric M Yeatman, "Energy harvesting piezoelectric wind speed sensor," Journal of Physics: Conference Series, vol. 1407, pp. 012--044, Nov 2019.
[3]
https://assistcenter.org/inertial-energy-harvesting/.
[4]
Z. J. Chew and M. Zhu, "Adaptive self-configurable rectifier for extended operating range of piezoelectric energy harvesting," IEEE Transactions on Industrial Electronics (TIE), vol. 67, no. 4, pp. 3267--3276, 2020.
[5]
M. Mangrulkar and S. G. Akojwar, "A simple and efficient solar energy harvesting for wireless sensor node," in ICRCICN'16, pp. 95--99.
[6]
A. Tobola, H. Leutheuser, M. Pollak, P. Spies, C. Hofmann, C. Weigand, B. M. Eskofier, and G. Fischer, "Self-powered multiparameter health sensor," IEEE journal of biomedical and health informatics, vol. 22, no. 1, pp. 15--22, 2018.
[7]
R. Shigeta, T. Sasaki, D. M. Quan, Y. Kawahara, R. J. Vyas, M. M. Tentzeris, and T. Asami, "Ambient rf energy harvesting sensor device with capacitor-leakage-aware duty cycle control," IEEE Sensors Journal, vol. 13, no. 8, pp. 2973--2983, 2013.
[8]
M. Gao, P. Wang, Y. Wang, and L. Yao, "Self-powered zigbee wireless sensor nodes for railway condition monitoring," IEEE TITS'18, vol. 19, no. 3, pp. 900--909.
[9]
M. Xie, C. Pan, J. Hu, C. Yang, and Y. Chen, "Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units," in ASP-DAC'15, pp. 316--321.
[10]
J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang, X. Li, H. Yang, and Y. Liu, "7.5 a 65nm 0.39-to-140.3tops/w 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1 × higher tops/mm2and 6t hbst-tram-based 2d data-reuse architecture," in ISSCC'19, pp. 138--140.
[11]
K. Qiu, N. Jao, M. Zhao, C. S. Mishra, G. Gudukbay, S. Jose, J. Sampson, M. T. Kandemir, and V. Narayanan, "Resirca: A resilient energy harvesting reram crossbar-based accelerator for intelligent embedded processors," in HPCA'20, pp. 315--327.
[12]
Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M.-F. Chiang, Y. Yan, B. Sai, and H. Yang, "A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops," in ESSCIRC'12, pp. 149--152.
[13]
X. Li, S. George, K. Ma, W. Tsai, A. Aziz, J. Sampson, S. K. Gupta, M. Chang, Y. Liu, S. Datta, and V. Narayanan, "Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops," TCAS-I'17, vol. 64, no. 11, pp. 2907--2919.
[14]
S. K. Thirumala, A. Raha, H. Jayakumar, K. Ma, V. Narayanan, V. Raghunathan, and S. K. Gupta, "Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems," in ISLPED'18, pp. 1--6.
[15]
Y. Liu, Z. Wang, A. Lee, F. Su, C. Lo, Z. Yuan, C. Lin, Q. Wei, Y. Wang, Y. King, C. Lin, P. Khalili, K. Wang, M. Chang, and H. Yang, "4.7 a 65nm reram-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic," in ISSCC'16, pp. 84--86.
[16]
A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King, C. Lin, H. Lee, P. Khalili Amiri, K. Wang, Y. Wang, H. Yang, Y. Liu, and M. Chang, "A reram-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors," JSSC'17, vol. 52, no. 8, pp. 2194--2207.
[17]
M. Qazi, A. Amerasekera, and A. P. Chandrakasan, "A 3.4-pj feram-enabled d flip-flop in 0.13-μ hboxm$ cmos for nonvolatile processing in digital systems," JSSC'14, vol. 49, no. 1, pp. 202--211.
[18]
"Texas instruments. [online]. available: www.ti.com/product/cc1101,"
[19]
F. Su, W. Chen, L. Xia, C. Lo, T. Tang, Z. Wang, K. Hsu, M. Cheng, J. Li, Y. Xie, Y. Wang, M. Chang, H. Yang, and Y. Liu, "A 462gops/j rram-based nonvolatile intelligent processor for energy harvesting ioe system featuring nonvolatile logics and processing-in-memory," in 2017 Symposium on VLSI Circuits, pp. C260--C261.
[20]
Y. Zha, E. Nowak, and J. Li, "Liquid silicon: A nonvolatile fully programmable processing-in-memory processor with monolithically integrated reram for big data/machine learning applications," in 2019 Symposium on VLSI Circuits, pp. C206--C207.
[21]
Y. Wang, Y. Liu, S. Li, X. Sheng, D. Zhang, M.-F. Chiang, B. Sai, X. Hu, and H. Yang, "PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors," TVLSI'13, vol. PP, no. 99, pp. 1491--1505.
[22]
A. Colin and B. Lucia, "Chain: tasks and channels for reliable intermittent programs," in Proc. ACM Program. Lang. (OOPSLA), vol. 51, pp. 514--530, 2016.
[23]
B. Lucia and B. Ransford, "A simpler, safer programming and execution model for intermittent systems," PLDI'15, vol. 50, no. 6, pp. 575--585.
[24]
M. Xie, M. Zhao, C. Pan, H. Li, Y. Liu, Y. Zhang, C. J. Xue, and J. Hu, "Checkpoint aware hybrid cache architecture for nv processor in energy harvesting powered systems," in CODES+ISSS'16, pp. 1--10, Oct.
[25]
H. Jayakumar, A. Raha, W. S. Lee, and V. Raghunathan, "Quickrecall: A hw/sw approach for computing across power cycles in transiently powered computers," JETC'15, vol. 12, no. 1.
[26]
K. Ma, Y. Zheng, S. Li, K. Swaminathan, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, "Architecture exploration for ambient energy harvesting nonvolatile processors," in HPCA'15, pp. 526--537.
[27]
T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. R. Yew, J. Y. Wu, C. C. Shuai, S. H. Wu, J. Myers, K. Doppler, M. Fujita, and S. Yamazaki, "Embedded memory and arm cortex-m0 core using 60-nm c-axis aligned crystalline indium--gallium--zinc oxide fet integrated with 65-nm si cmos," JSSC'17, vol. 52, no. 4, pp. 925--932.
[28]
C. Ding, S. Liao, Y. Wang, Z. Li, N. Liu, Y. Zhuo, C. Wang, X. Qian, Y. Bai, G. Yuan, X. Ma, Y. Zhang, J. Tang, Q. Qiu, X. Lin, and B. Yuan, "CirCNN: Accelerating and compressing deep neural networks using block-circulant weight matrices," in MICRO'17, p. 395--408.
[29]
M. Xie, C. Pan, J. Hu, C. J. Xue, and Q. Zhuge, "Non-volatile registers aware instruction selection for embedded systems," in RTCSA'14, pp. 1--9.
[30]
Q. Li, M. Zhao, J. Hu, Y. Liu, Y. He, and C. J. Xue, "Compiler directed automatic stack trimming for efficient non-volatile processors," in DAC'15, pp. 1--6.
[31]
W. Song, Y. Zhou, M. Zhao, L. Ju, C. J. Xue, and Z. Jia, "EMC: Energy-aware morphable cache design for non-volatile processors," TC'19, vol. 68, no. 4, pp. 498--509.
[32]
K. Maeng and B. Lucia, "Adaptive dynamic checkpointing for safe efficient intermittent computing," in OSDI'18, pp. 129--144.
[33]
B. Ransford, S. S. Clark, M. Salajegheh, and K. Fu, "Getting things done on computational rfids with energy-aware checkpointing and voltage-aware scheduling," in Proceedings of the 2008 Conference on Power Aware Computing and Systems, pp. 5--5.
[34]
M. Zhao, C. Fu, Z. Li, Q. Li, M. Xie, Y. Liu, J. Hu, Z. Jia, and C. J. Xue, "Stack-size sensitive on-chip memory backup for self-powered nonvolatile processors," TCAD'17, vol. 36, no. 11, pp. 1804--1816.
[35]
J. Li, M. Zhao, L. Ju, C. J. Xue, and Z. Jia, "Maximizing forward progress with cache-aware backup for self-powered non-volatile processors," in DAC'17, pp. 1--6.
[36]
W. Fan, Y. Zhang, W. Song, M. Zhao, Z. Shen, and Z. Jia, "Q-learning based backup for energy harvesting powered embedded systems," in DATE'20, pp. 1247--1252.
[37]
B. Ransford and B. Lucia, "Nonvolatile memory is a broken time machine," in Proceedings of the workshop on MMSPC'14, pp. 1--3.
[38]
M. Xie, M. Zhao, C. Pan, J. Hu, Y. Liu, and C. J. Xue, "Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor," in DAC'15, pp. 184:1--184:6.
[39]
M. Surbatovich, L. Jia, and B. Lucia, "I/O dependent idempotence bugs in intermittent systems," Proc. ACM Program. Lang. (OOPSLA), vol. 3, 2019.
[40]
W.-M. Chen, T.-S. Cheng, P.-C. Hsiu, and T.-W. Kuo, "Value-Based Task Scheduling for Nonvolatile Processor-Based Embedded Devices," in RTSS'16, pp. 247--256.
[41]
W.-M. Chen, P.-C. Hsiu, and T.-W. Kuo, "Enabling Failure-resilient Intermittently-powered Systems Without Runtime Checkpointing," in DAC'19, pp. 104:1--6.
[42]
W.-M. Chen, Y.-T. Chen, P.-C. Hsiu, and T.-W. Kuo, "Multiversion Concurrency Control on Intermittent Systems," in ICCAD'19, pp. 1--8.
[43]
W.-M. Chen, T.-W. Kuo, and P.-C. Hsiu, "Enabling failure-resilient intermittent systems without runtime checkpointing," TCAD'20, Early Access.
[44]
https://github.com/EMCLab-Sinica/Intermittent-OS/.
[45]
K. Maeng, A. Colin, and B. Lucia, "Alpaca: Intermittent execution without checkpoints," Proc. ACM Program. Lang. (OOPSLA), vol. 1, 2017.
[46]
K. Maeng and B. Lucia, "Adaptive low-overhead scheduling for periodic and reactive intermittent execution," in PLDI'20, p. 1005--1021.
[47]
A. Colin, E. Ruppel, and B. Lucia, "A reconfigurable energy storage architecture for energy-harvesting devices," in ASPLOS'18, pp. 767--781.
[48]
K. Ma, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, "Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile," in ICCAD'15, pp. 670--675.
[49]
K. Ma, X. Li, S. R. Srinivasa, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, "Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors," in ASP-DAC'17, pp. 678--683.
[50]
K. Ma, X. Li, J. Li, Y. Liu, Y. Xie, J. Sampson, M. T. Kandemir, and V. Narayanan, "Incidental computing on iot nonvolatile processors," in MICRO'17, pp. 204--218.
[51]
K. Ma, J. Li, X. Li, Y. Liu, Y. Xie, M. Kandemir, J. Sampson, and V. Narayanan, "Iaa: Incidental approximate architectures for extremely energy-constrained energy harvesting scenarios using iot nonvolatile processors," IEEE Micro'18, vol. 38, no. 4, pp. 11--19.
[52]
K. Ma, X. Li, M. T. Kandemir, J. Sampson, V. Narayanan, J. Li, T. Wu, Z. Wang, Y. Liu, and Y. Xie, "NEOFog: Nonvolatility-exploiting optimizations for fog computing," in ASPLOS'18, pp. 782--796.
[53]
A. Y. Majid, C. D. Donne, K. Maeng, A. Colin, K. S. Yildirim, B. Lucia, and P. Pawełczak, "Dynamic task-based intermittent execution for energy-harvesting devices," TSN'20, vol. 16, no. 1.
[54]
B. L. Graham Gobieski, Nathan Beckmann, "Intermittent deep neural network inference," in SysML Conference, pp. 1--3, 2018.
[55]
G. Gobieski, B. Lucia, and N. Beckmann, "Intelligence beyond the edge: Inference on intermittent embedded systems," in ASPLOS '19, p. 199--213, 2019.

Cited By

View all
  • (2024)TVTAC: Triple Voltage Threshold Approximate Cache for Energy Harvesting Nonvolatile ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340694243:12(4546-4557)Online publication date: Dec-2024
  • (2023)Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent ComputingACM Transactions on Architecture and Code Optimization10.1145/362952420:4(1-25)Online publication date: 20-Oct-2023
  • (2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
  • Show More Cited By

Index Terms

  1. Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Other conferences
    GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
    September 2020
    597 pages
    ISBN:9781450379441
    DOI:10.1145/3386263
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 07 September 2020

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. PIM
    2. architecture
    3. checkpointing
    4. energy harvesting
    5. non-volatile processor
    6. task scheduling

    Qualifiers

    • Research-article

    Funding Sources

    • National Natural Science Foundation of China

    Conference

    GLSVLSI '20
    GLSVLSI '20: Great Lakes Symposium on VLSI 2020
    September 7 - 9, 2020
    Virtual Event, China

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)28
    • Downloads (Last 6 weeks)2
    Reflects downloads up to 22 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)TVTAC: Triple Voltage Threshold Approximate Cache for Energy Harvesting Nonvolatile ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340694243:12(4546-4557)Online publication date: Dec-2024
    • (2023)Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent ComputingACM Transactions on Architecture and Code Optimization10.1145/362952420:4(1-25)Online publication date: 20-Oct-2023
    • (2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
    • (2023)Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-VIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316910842:1(82-94)Online publication date: Jan-2023
    • (2022)Intermittent-Aware Distributed Concurrency ControlIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319750241:11(3721-3732)Online publication date: Nov-2022
    • (2022)Transient computing for energy harvesting systems: A surveyJournal of Systems Architecture10.1016/j.sysarc.2022.102743132(102743)Online publication date: Nov-2022
    • (2022)A survey and experimental analysis of checkpointing techniques for energy harvesting devicesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102464126:COnline publication date: 23-May-2022

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media