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A New Silicon-aware Big Data SoC Timing Analysis Solution: A Case Study of Empyrean University Program

Published: 07 September 2020 Publication History

Abstract

With advanced IC process nodes, traditional corner-based timing sign-off methods are facing big challenges. Although STA tools have incorporated more sophisticated models such as AOCV/ POCV/LVF to characterize variation effects, they can still lead to excessive pessimism or incomplete coverage [1]. To consider the effects of variation on reliability, designers need to find a more potent solution. Now Huada Empyrean has raised a smart new approach which can provide a fast timing analysis solution with SPICE accuracy. It can fill the gap between STA and silicon for advanced process nodes, especially for ultra-low-voltage designs that are used in AI/IoT/Blockchain applications. Theories and algorithms supplied by some top universities, which joined a long-term Empyrean University Program, have made great contributions to the R&D process of this solution.

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Universities such as Tsinghua University of Peking University build demonstration microelectronics College, http://www.360doc.com/content/18/0525/01/12113693_756806944.shtml
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cover image ACM Other conferences
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 September 2020

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Author Tags

  1. empyrean university program
  2. process variation
  3. sta
  4. timing sign-off

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GLSVLSI '20
GLSVLSI '20: Great Lakes Symposium on VLSI 2020
September 7 - 9, 2020
Virtual Event, China

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