Yoonah Paik
Seon Wook Kim
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Abstract
Dynamic Random Access Memory (DRAM) standards have evolved for higher bandwidth, larger capacity, and lower power consumption, so their specifications have become complicated to satisfy the design goals. These complex implementations have significantly increased the test time overhead for design verification; thus, a tremendous amount of command sequences are used. However, since the sequences generated by real machines or memory simulators are the results of scheduling for high performance, they result in low test coverage with repetitive patterns. Eventually, various workloads should be applied to increase the coverage, but this approach incurs significant test time overhead. A few preliminary studies have been proposed to generate predefined or random sequences to cover various test cases or increase test coverage. However, they have limitations in representing various memory behaviors of real workloads.
In this article, we define a performance metric for estimating the test coverage when using command sequences. Then, our experiment shows that the coverage of a real machine and a simulator is low and similar. Also, the coverage patterns are almost the same in all tested benchmarks. To alleviate the problem, we propose a test-oriented command scheduling algorithm that increases the test coverage while preserving the memory behaviors of workloads and reducing the test time overhead by extracting representative sequences based on the similarity between command sequences. For the sequence extraction and the coverage estimation, our test sequences are embedded into vectors using bag-of-Ngrams. Compared to the simulator, our algorithm achieves 2.94x higher coverage while reducing the test overhead to 7.57%.
- Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi. 2015. A scalable processing-in-memory accelerator for parallel graph processing. In Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA’15). Portland, Oregon, 105--117. DOI:https://doi.org/10.1145/2749469.2750386Google Scholar
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- Barbara Aichinger. 2015. DDR memory errors caused by row hammer. In Proceedings of 2015 IEEE High Performance Extreme Computing Conference (HPEC’15). Waltham, MA, 1--5.Google ScholarCross Ref
- JEDEC Solid State Technology Association. 2004. Double Data Rate (DDR) SDRAM Specification. https://www.jedec.org/sites/default/files/docs/JESD79F.pdf.Google Scholar
- JEDEC Solid State Technology Association. 2008. DDR2 SDRAM Standard. https://www.jedec.org/sites/default/files/docs/JESD79-2E.pdf.Google Scholar
- JEDEC Solid State Technology Association. 2012. DDR3 SDRAM Standard. https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf.Google Scholar
- JEDEC Solid State Technology Association. 2013. DDR4 SDRAM STANDARD. https://www.jedec.org/sites/default/files/docs/JESD79-4.pdf.Google Scholar
- JEDEC Solid State Technology Association. 2014. Low Power Double Data Rate 4 SDRAM (LPDDR4). https://www.jedec.org/standards-documents/docs/JESD209-4B.Google Scholar
- JEDEC Solid State Technology Association. 2018. High Bandwidth Memory (HBM) DRAM. https://www.jedec.org/standards-documents/docs/jesd235a.Google Scholar
- Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, and Todd Austin. 2016. ANVIL: Software-based protection against next-generation rowhammer attacks. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’16). Atlanta, Georgia, 743--755. DOI:https://doi.org/10.1145/2872362.2872390Google ScholarDigital Library
- Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The gem5 simulator. SIGARCH Computer Architecture News 39, 2 (Aug. 2011), 1--7. DOI:https://doi.org/10.1145/2024716.2024718Google ScholarDigital Library
- Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and Onur Mutlu. 2018. Google workloads for consumer devices: Mitigating data movement bottlenecks. In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’18). Williamsburg, VA, 316--331. DOI:https://doi.org/10.1145/3173162.3173177Google ScholarDigital Library
- William B. Cavnar and John M. Trenkle. 1994. N-gram-based text categorization. In Proceedings of the 3rd Annual Symposium on Document Analysis and Information Retrieval (SDAIR’94). Las Vegas, NV, 161--175.Google Scholar
- Kevin K. Chang, A. Giray Yağlçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O’Connor, Hasan Hassan, and Onur Mutlu. 2017. Understanding reduced-voltage operation in modern dram devices: Experimental characterization, analysis, and mechanisms. Proceedings of the ACM on Measurement and Analysis of Computing Systems 1, 1, Article 10 (June 2017), 42 pages. DOI:https://doi.org/10.1145/3084447Google ScholarDigital Library
- Krishnendu Chatterjee, Rasmus Ibsen-Jensen, and Rupak Majumdar. 2014. Edit distance for timed automata. In Proceedings of the 17th International Conference on Hybrid Systems: Computation and Control (HSCC’14). Berlin, Germany, 303--312. DOI:https://doi.org/10.1145/2562059.2562141Google ScholarDigital Library
- Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi. 2012. Staged reads: Mitigating the impact of DRAM writes on DRAM reads. In Proceedings of the 18th IEEE Symposium on High Performance Computer Architecture (HPCA’12). New Orleans, LA, 1--12. DOI:https://doi.org/10.1109/HPCA.2012.6168943Google ScholarDigital Library
- Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In Proceedings of the 43rd Annual International Symposium on Computer Architecture (ISCA’16). Seoul, Republic of Korea, 27--39. DOI:https://doi.org/10.1109/ISCA.2016.13Google ScholarDigital Library
- Keewon Cho, Wooheon Kang, Hyungjun Cho, Changwook Lee, and Sungho Kang. 2016. A survey of repair analysis algorithms for memories. ACM Computing Surveys (CSUR) 49, 3, Article 47 (Oct. 2016), 41 pages. DOI:https://doi.org/10.1145/2971481Google Scholar
- Standard Performance Evaluation Corporation. 2006. SPEC CPU 2006. Retrieved from https://www.spec.org/cpu2006/.Google Scholar
- Robert H. Dennard. 1968. Field-effect Transistor Memory. US Patent 3,387,286.Google Scholar
- Christopher A. Flores, Rosa L. Figueroa, and Jorge E. Pezoa. 2019. FREGEX: A feature extraction method for biomedical text classification using regular expressions. In Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’19). 6085--6088. DOI:https://doi.org/10.1109/EMBC.2019.8857471Google Scholar
- Bernhard Haeupler, Aviad Rubinstein, and Amirbehshad Shahrasbi. 2019. Near-linear time insertion-deletion codes and (1+ϵ)-approximating edit distance via indexing. In Proceedings of the 51st Annual ACM SIGACT Symposium on Theory of Computing (STOC’19). Phoenix, AZ, 697--708. DOI:https://doi.org/10.1145/3313276.3316371Google ScholarDigital Library
- Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu. 2017. SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies. In Proceedings of the 23rd IEEE Symposium on High Performance Computer Architecture (HPCA’17). Austin, TX, 241--252. DOI:https://doi.org/10.1109/HPCA.2017.62Google ScholarCross Ref
- Mohamed Hassan and Hiren Patel. 2018. MCXplore: Automating the validation process of dram memory controller designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 5 (May 2018), 1050--1063. DOI:https://doi.org/10.1109/TCAD.2017.2705123Google Scholar
- J. R. Huang, C. K. Ong, K. T. Cheng, and C. W. Wu. 2000. An FPGA-based re-configurable functional tester for memory chips. In Proceedings of the 9th Asian Test Symposium. 51--57. DOI:https://doi.org/10.1109/ATS.2000.893602Google ScholarCross Ref
- Intel. 2003. Intel Platform and Component Validation: A Commitment to Quality, Reliability and Compatibility. Retrieved from http://www.intel.com/design/chipsets/labtour/pvpt_whitepaper.html.Google Scholar
- Jaeyung Jun, Kyu Hyun Choi, Hokwon Kim, Sang Ho Yu, Seon Wook Kim, and Youngsun Han. 2017. Recovering from biased distribution of faulty cells in memory by reorganizing replacement regions through universal hashing. ACM Transactions on Design Automation of Electronic Systems (TODAES) 23, 2, Article 16 (Oct. 2017), 21 pages. DOI:https://doi.org/10.1145/3131241Google Scholar
- Jaeyung Jun, Yoonah Paik, Gyeong Il Min, Seon Wook Kim, and Youngsun Han. 2019. Fault tolerance technique offlining faulty blocks by heap memory management. ACM Transactions on Design Automation of Electronic Systems (TODAES) 24, 4, Article 47 (June 2019), 25 pages. DOI:https://doi.org/10.1145/3329079Google ScholarDigital Library
- Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, and Onur Mutlu. 2017. Detecting and mitigating data-dependent DRAM failures by exploiting current memory content. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’17). Cambridge, Massachusetts, 27--40. DOI:https://doi.org/10.1145/3123939.3123945Google ScholarDigital Library
- Moonsoo Kim, Jungwoo Choi, Hyun Kim, and Hyuk-Jae Lee. 2019. An effective DRAM address remapping for mitigating rowhammer errors. IEEE Trans. Comput. 68, 10 (Oct. 2019), 1428--1441.Google ScholarCross Ref
- Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. In Proceedings of the 41st Annual International Symposium on Computer Architecuture (ISCA’14). Minneapolis, Minnesota, 361--372. http://dl.acm.org/citation.cfm?id=2665671.2665726Google ScholarDigital Library
- Yoongu Kim, Weikun Yang, and Onur Mutlu. 2016. Ramulator: A fast and extensible DRAM simulator. IEEE Computer Architecture Letters 15, 1 (Jan. 2016), 45--49. DOI:https://doi.org/10.1109/LCA.2015.2414456Google ScholarDigital Library
- Radhesh Krishnan Konoth, Marco Oliverio, Andrei Tatar, Dennis Andriesse, Herbert Bos, Cristiano Giuffrida, and Kaveh Razavi. 2018. ZebRAM: Comprehensive and compatible software protection against rowhammer attacks. In Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI’18). Carlsbad, CA, 697--710.Google Scholar
- Eojin Lee, Sukhan Lee, G. Edward Suh, and Jung Ho Ahn. 2018. TWiCe: Time window counter based row refresh to prevent row-hammering. IEEE Computer Architecture Letters 17, 1 (Jan. 2018), 96--99.Google ScholarDigital Library
- Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Jongsun Park, Il Park, and Seon Wook Kim. 2019. Design of processing-“inside”-memory optimized for DRAM behaviors. IEEE Access 7 (June 2019), 82633--82648. DOI:https://doi.org/10.1109/ACCESS.2019.2924240Google Scholar
- Huma Lodhi, Craig Saunders, John Shawe-Taylor, Nello Cristianini, and Chris Watkins. 2002. Text classification using string kernels. Journal of Machine Learning Research 2, Feb (Feb. 2002), 419--444.Google Scholar
- Tomas Mikolov, Kai Chen, Greg Corrado, and Jeffrey Dean. 2013. Efficient estimation of word representations in vector space. In Workshop on 2013 International Conference on Learning Representations Workshop (ICLR’13). Toulon, France.Google Scholar
- Prabhat Mishra, Sandip Ray, Ronny Morad, and Avi Ziv. 2017. Post-Silicon Validation in the soc era: A tutorial introduction. IEEE Design 8 Test 34, 3 (June 2017), 68--92. DOI:https://doi.org/10.1109/MDAT.2017.2691348Google Scholar
- Joung-Wook Moon, Hye-Sung Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki-Jae Song, et al. 2018. An enhanced built-off-test transceiver with wide-range, self-calibration engine for 3.2 Gb/s/pin DDR4 SDRAM. In Proceedings of 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC’18). Tainan, Taiwan, 139--142.Google ScholarCross Ref
- Onur Mutlu. 2017. The RowHammer problem and other issues we may face as memory becomes denser. In Proceedings of the Conference on Design, Automation 8 Test in Europe (DATE’17). Lausanne, Switzerland, 1116--1121. http://dl.acm.org/citation.cfm?id=3130379.3130643Google ScholarCross Ref
- Saul B. Needleman and Christian D. Wunsch. 1970. A general method applicable to the search for similarities in the amino acid sequence of two proteins. Journal of Molecular Biology 48, 3 (March 1970), 443--453. DOI:https://doi.org/10.1016/0022-2836(70)90057-4Google ScholarCross Ref
- Duy-Thanh Nguyen, Nhut-Minh Ho, and Ik-Joon Chang. 2019. St-DRC: Stretchable DRAM refresh controller with no parity-overhead error correction scheme for energy-efficient DNNs. In Proceedings of the 56th Annual Design Automation Conference (DAC’19). Las Vegas, NV, Article 205, 6 pages. DOI:https://doi.org/10.1145/3316781.3317915Google ScholarDigital Library
- Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seunghoon Oh, Su-Yeon Doo, ChangYong Lee Hyoung-Joo Kim, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, YoungRyeol Choi, Yong-Cheol Bae Young-Chul Cho, Taeseong Jang, Chulsung Park, Kwangil Park, SeongJin Jang, and Joo Sun Choi. 2015. A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With integrated ECC engine for sub-1 V DRAM core operation. IEEE Journal of Solid-State Circuits 50, 1 (Jan. 2015), 178--190. DOI:https://doi.org/10.1109/JSSC.2014.2353799Google ScholarCross Ref
- Varnavas Papaioannou and Nicolas Courtois. 2017. On feasibility and performance of rowhammmer attack. In Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security (ASHES’17). Dallas, Texas, 53--58. DOI:https://doi.org/10.1145/3139324.3139330Google ScholarDigital Library
- Avadh Patel, Furat Afram, Shunfei Chen, and Kanad Ghose. 2011. MARSS: A full system simulator for multicore x86 CPUs. In Proceedings of the 48th Annual Design Automation Conference (DAC’11). San Diego, CA, 1050--1055.Google ScholarDigital Library
- Konrad Rieck. 2011. Similarity measures for sequential data. Wiley Interdisciplinary Reviews: Data Mining and Knowledge Discovery 1, 4 (May 2011), 296--304.Google ScholarDigital Library
- Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE Computer Architecture Letters 10, 1 (Jan. 2011), 16--19.Google ScholarDigital Library
- T. F. Smith and M. S. Waterman. 1981. Identification of common molecular subsequences. Journal of Molecular Biology 147, 1 (March 1981), 195--197. DOI:https://doi.org/10.1016/0022-2836(81)90087-5Google ScholarCross Ref
- Stephen Sunter and Aubin Roy. 2007. A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes. In Proceedings of the 2007 IEEE International Test Conference. Santa Clara, CA, 1--8.Google ScholarCross Ref
- B. M. S. Bahar Talukder, Joseph Kerns, Biswajit Ray, Thomas Morris, and Md. Tauhidur Rahman. 2019. Exploiting DRAM latency variations for generating true random numbers. In Proceedings of the 37th IEEE International Conference on Consumer Electronics (ICCE’19). Las Vegas, NV, 1--6. DOI:https://doi.org/10.1109/ICCE.2019.8662060Google ScholarCross Ref
- Victor van der Veen, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clementine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida. 2016. Drammer: Deterministic rowhammer attacks on mobile platforms. In Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security (CCS’16). Vienna, Austria, 1675--1689. DOI:https://doi.org/10.1145/2976749.2978406Google ScholarDigital Library
- Felipe Viegas, Washington Luiz, Christian Gomes, Amir Khatibi, Sérgio Canuto, Fernando Mourão, Thiago Salles, Leonardo Rocha, and Marcos André Gonçalves. 2018. Semantically-enhanced topic modeling. In Proceedings of the 27th ACM International Conference on Information and Knowledge Management (CIKM’18). Torino, Italy, 893--902. DOI:https://doi.org/10.1145/3269206.3271797Google ScholarDigital Library
- Ran Wang, Krishnendu Chakrabarty, and Sudipta Bhawmik. 2015. Built-in self-test and test scheduling for interposer-based 2.5D IC. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 4, Article 58 (Sept. 2015), 24 pages. DOI:https://doi.org/10.1145/2757278Google ScholarDigital Library
- Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, and Yung-Fa Chou. 2018. A channel-sharable built-in self-test scheme for multi-channel DRAMs. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASPDAC’18). Jeju, Republic of Korea, 245--250. http://dl.acm.org/citation.cfm?id=3201607.3201658Google ScholarDigital Library
- Xin-Chuan Wu, Timothy Sherwood, Frederic T. Chong, and Yanjing Li. 2019. Protecting page tables from rowhammer attacks using monotonic pointers in DRAM true-cells. In Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’19). Providence, RI, 645--657. DOI:https://doi.org/10.1145/3297858.3304039Google ScholarDigital Library
- Hao Yu Yang, Shih Hua Kuo, Tzu Hsuan Huang, Chi Hung Chen, Chris Lin, and Mango C. T. Chao. 2015. Random pattern generation for post-silicon validation of DDR3 SDRAM. In Proceedings of the IEEE 33rd VLSI Test Symposium (VTS’15). Napa, CA, 1--6. DOI:https://doi.org/10.1109/VTS.2015.7116287Google Scholar
Index Terms
- Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead
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