research-article

A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC

Authors:

Yongpan LiuAuthors Info & Claims

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

Pages 126 - 131

https://doi.org/10.1145/3394885.3431521

Published: 29 January 2021 Publication History

Get Access

Abstract

Nowadays, deep neural network (DNN) has played an important role in machine learning. Non-volatile computingin-memory (nvCIM) for DNN has become a new architecture to optimize hardware performance and energy efficiency. However, the existing nvCIM accelerators focus on system-level performance but ignore analog factors. In this paper, the sense margin and offset are considered in the proposed nvCIM framework. The margin enhancement based current-mode sense amplifier (MECSA) and the offset reduction based analog-to-digital converter (ORADC) are proposed to improve the accuracy of the ADC. Based on the above methods, the nvCIM framework is displayed and the experiment results show that the proposed framework has an improvement on area, power, and latency with the high accuracy of network models, and the energy efficiency is 2.3 - 20.4x compared to the existing RRAM based nvCIM accelerators.

References

[1]

P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie. Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pages 27--39, 2016.

Digital Library

Google Scholar

[2]

A. Shafiee, A. Nag, N. Muralimanohar, R. Balasubramonian, J. P. Strachan, M. Hu, R. S. Williams, and V. Srikumar. Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pages 14--26, 2016.

Digital Library

Google Scholar

[3]

L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. Mnsim: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pages 469--474, 2016.

Google Scholar

[4]

M. Chang, S. Shen, C. Liu, C. Wu, Y. Lin, S. Wu, C. Huang, H. Lai, Y. King, C. Lin, H. Liao, Y. Chih, and H. Yamauchi. An offset-tolerant current-sampling-based sense amplifier for sub-100na-cell-current nonvolatile memory. In 2011 IEEE International Solid-State Circuits Conference - (ISSCC), pages 206--208, 2011.

Crossref

Google Scholar

[5]

W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang, T. Hsu, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. A 65nm 1mb nonvolatile computing-inmemory reram macro with sub-16ns multiply-and-accumulate for binary dnn ai edge processors. In 2018 IEEE International Solid - State Circuits Conference - (ISSCC), pages 494--496, 2018.

Crossref

Google Scholar

[6]

C. Lo, W. Lin, W. Lin, H. Lin, T. Yang, Y. Chiang, Y. King, C. Lin, Y. Chih, T. J. Chang, and M. Chang. A reram macro using dynamic trip-point-mismatch sampling current-mode sense amplifier and low-dc voltage-mode write-termination scheme against resistance and write-delay variation. IEEE Journal of Solid-State Circuits, 54(2):584--595, 2019.

Crossref

Google Scholar

[7]

C. Xue, W. Chen, J. Liu, J. Li, W. Lin, W. Lin, J. Wang, W. Wei, T. Chang, T. Chang, T. Huang, H. Kao, S. Wei, Y. Chiu, C. Lee, C. Lo, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. A 1mb multibit reram computing-in-memory macro with 14.6ns parallel mac computing time for cnn based ai edge processors. In 2019 IEEE International Solid- State Circuits Conference - (ISSCC), pages 388--390, 2019.

Crossref

Google Scholar

[8]

Y. Lecun, L. Bottou, Y. Bengio, and P. Haffner. Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86(11):2278--2324, 1998.

Crossref

Google Scholar

[9]

A. Krizhevsky, I. Sutskever, and G. Hinton. Imagenet classification with deep convolutional neural networks. In Proceedings of the 25th International Conference on Neural Information Processing Systems, volume 1, pages 1097--1105, 2012.

Google Scholar

[10]

S. Karen and Z. Andrew. Very deep convolutional networks for large-scale image recognition. Computer Science, 2014.

Google Scholar

[11]

C. Xue, W. Chen, J. Liu, J. Li, W. Lin, W. Lin, J. Wang, W. Wei, T. Huang, T. Chang, T. Chang, H. Kao, Y. Chiu, C. Lee, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. Embedded 1-mb reram-based computing-in-memory macro with multibit input and weight for cnn-based ai edge processors. IEEE Journal of Solid-State Circuits, 55(1):203--215, 2020.

Crossref

Google Scholar

[12]

Z. Zhu, H. Sun, Y. Lin, G. Dai, L. Xia, S. Han, Y. Wang, and H. Yang. A configurable multi-precision cnn computing framework based on single bit rram. In 2019 56th ACM/IEEE Design Automation Conference (DAC), pages 1--6, 2019.

Digital Library

Google Scholar

Cited By

View all

Huang YHe YYue JYang HLiu Y(2022)Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory SystemsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.312455369:2(518-529)Online publication date: Feb-2022
https://doi.org/10.1109/TCSI.2021.3124553

Index Terms

A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Neural networks

Recommendations

Offset-injection digital background calibration for VCO-based ADC

A new offset-injection digital background calibration technique for VCO-based ADC is proposed to compensate for VCO nonlinearity. By injecting a predetermined offset signal, the new technique suppresses in-band distortions caused by VCO nonlinearity ...
A 0.8-μW window SAR ADC with offset cancellation for digital DC---DC converters

This letter presents the design of a window successive approximation (SAR) analog-to-digital converter (ADC) using an ultra-fast, offset-cancelled auto-zero comparator for digital DC---DC converters. It is designed in a standard CMOS 0.18 μm process. ...
Iterative gain enhancement in a power-efficient algorithmic adc

Comments

Information & Contributors

Information

Published In

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

January 2021

930 pages

ISBN:9781450379991

DOI:10.1145/3394885

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 January 2021

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Funding Sources

Beijing Innovation Center for Future Chip
National Key Research and Development Program of China
Beijing National Research Center For Information Science And Technology
National Natural Science Foundation of China

Conference

ASPDAC '21

Sponsor:

SIGDA

ASPDAC '21: 26th Asia and South Pacific Design Automation Conference

January 18 - 21, 2021

Tokyo, Japan

Acceptance Rates

ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
150
Total Downloads

Downloads (Last 12 months)18
Downloads (Last 6 weeks)0

Reflects downloads up to 28 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Huang YHe YYue JYang HLiu Y(2022)Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory SystemsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.312455369:2(518-529)Online publication date: Feb-2022
https://doi.org/10.1109/TCSI.2021.3124553

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Offset-injection digital background calibration for VCO-based ADC

A 0.8-μW window SAR ADC with offset cancellation for digital DC---DC converters

Iterative gain enhancement in a power-efficient algorithmic adc

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Funding Sources

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations