Jianqi Chen
ABSTRACT
The protection of Intellectual Property (IP) has emerged as one of the most important issues in the hardware design industry. Most VLSI design companies are now fabless and need to protect their IP from being illegally distributed. One of the main approach to address this has been through logic locking. Logic locking prevents IPs from being reversed engineered as well as overbuilding the hardware circuit by untrusted foundries. One of the main problem with existing logic locking techniques is that the foundry has full access to the entire design including the logic locking mechanism. Because of the importance of this topic, continuous more robust locking mechanisms are proposed and equally fast new methods to break them appear. One alternative approach is to lock a circuit through omission. The main idea is to selectively map a portion of the IP onto an embedded FPGA (eFPGA). Because the foundry does not have access to the bitstream, the circuit cannot be used until programmed by the legitimate user. One of the main problems with this approach is the large overhead in terms of area and power, as well as timing degradation. Area is especially a concern for price sensitive applications. To address this, in this work we presents a method to map portions of a design onto a Coarse Grained Runtime Reconfigurable Architecture (CGRRA) such that multiple parts of a design can be hidden onto the CGRRA, substantially amortizing the area overhead introduced by the CGRRA.
- A. Balachandran and B Carrion Schafer. 2020. Efficient Functional Locking of Behavioral IPs. In MWCAS. 639--642.Google Scholar
- Benjamin Carrion Schafer and Anushree Mahapatra. 2014. S2CBench: Synthesizable System C Benchmark Suite. IEEE Embedded Systems Letters 6, 3 (2014), 53--56.Google ScholarCross Ref
- R. S. Chakraborty and S. Bhunia. 2009. HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. IEEE TCAD 28, 10 (Oct 2009), 1493--1502.Google Scholar
- Renesas Electronics. 2020. Stream Transpose Processor. Retrieved June 2, 2020 from https://www.renesas.com/us/en/products/power-management/pmic/stp-engine.htmlGoogle Scholar
- T. Hoque, R. S. Chakraborty, and S. Bhunia. 2020. Hardware Obfuscation and Logic Locking: A Tutorial Introduction. IEEE Design Test 37, 3 (2020), 59--77.Google ScholarCross Ref
- Changmoo Kim, Moo-Kyoung Chung, Yeon-Gon Cho, Mario Konijnenburg, Soojung Ryu, and Jeongwook Kim. 2012. ULP-SRP: Ultra low power Samsung Re-configurable Processor for biomedical applications. 2012 International Conference on Field-Programmable Technology (2012), 329--334.Google ScholarCross Ref
- I. Kuon and J. Rose. 2007. Measuring the Gap Between FPGAs and ASICs. IEEE TCAD 26, 2 (2007), 203--215.Google ScholarDigital Library
- Bao Liu et al. 2014. Embedded Reconfigurable Logic for ASIC Design Obfuscation Against Supply Chain Attacks. In DATE. 243:1--243:6.Google Scholar
- Christian Pilato, Francesco Regazzoni, Ramesh Karri, and Siddharth Garg. 2018. TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis (DAC '18). Association for Computing Machinery, New York, NY, USA, Article 155, 6 pages.Google Scholar
- Christian Pilato, Kaijie Wu, Siddharth Garg, Ramesh Karri, and Francesco Regazzoni. 2019. TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38, 5 (2019), 798--808.Google ScholarCross Ref
- J. Rajendran, O. Sinanoglu, and R. Karri. 2013. Is split manufacturing secure?. In DATE. 1259--1264.Google Scholar
- Jarrod A. Roy et al. 2008. EPIC: Ending Piracy of Integrated Circuits. In DATE. 1069--1074.Google Scholar
- M. M. Shihab et al. 2019. Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. In DATE. 528--533.Google Scholar
- T. Winograd et al. 2016. Hybrid STT-CMOS designs for reverse-engineering prevention. In DAC. 1--6.Google Scholar
- Henry Wong, Vaughn Betz, and Jonathan Rose. 2011. Comparing FPGA vs. Custom Cmos and the Impact on Processor Microarchitecture. In FPGA. ACM, 5--14.Google Scholar
- Muhammad Yasin et al. 2017. What to Lock? Functional and Parametric Locking. In GLSVLSI. ACM, New York, NY, USA, 351--356. https://doi.org/10.1145/3060403.3060492Google Scholar
- J. Zhang. 2016. A Practical Logic Obfuscation Technique for Hardware Security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 3 (2016), 1193--1197.Google ScholarDigital Library
Index Terms
- Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures
Recommendations
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy
Modern embedded systems, to accommodate different applications or functionalities over the same substrate and provide flexibility at the hardware level, are often resource redundant and, consequently, power hungry. Therefore, dedicated design frameworks ...
Low Power Consumption Coarse Grained Reconfigurable Adder
ICCEE '09: Proceedings of the 2009 Second International Conference on Computer and Electrical Engineering - Volume 02Reconfigurable architecture gives the advantage of both high performance and high flexibility. However power consumption is also an important criterion which determines the efficiency of the reconfigurable architecture to be used in data intensive ...
Binary acceleration using coarse-grained reconfigurable architecture
Coarse-grained reconfigurable architectures (CGRAs) have been well-researched and shown to be particularly effective in acceleration of data-intensive applications. However, practical difficulties in application mapping have hindered their widespread ...
Comments