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A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS

Published: 29 January 2021 Publication History

Abstract

A 3D-stacked SRAM using an inductive coupling wireless inter-chip communication technology (TCI) is presented for an AI inference accelerator. The energy and area efficiency are improved thanks to the introduction of a proposed low-voltage NMOS push-pull transmitter and a 12:1 SerDes. A termination scheme to short unused open coils is proposed to eliminate the ringing in an inductive coupling bus. Test chips were fabricated in a 40-nm CMOS technology confirming 0.40-V operation of the proposed transmitter with successful stacked SRAM operation.

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K. Sohn et al., IEEE JSSC, Jan. 2017.
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D. U. Lee et al., IEEE JSSC, Jan. 2015.
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K. Ueyoshi et al., IEEE JSSC, Jan. 2019.
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N. Miura et al., IEEE JSSC, Mar. 2009.
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L.-C. Hsu et al., ASP-DAC, Jan. 2016.
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Cited By

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  • (2023)A Survey of Memory-Centric Energy Efficient Computer ArchitectureIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.329759534:10(2657-2670)Online publication date: Oct-2023
  • (2023)3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323675(1-9)Online publication date: 28-Oct-2023

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cover image ACM Conferences
ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference
January 2021
930 pages
ISBN:9781450379991
DOI:10.1145/3394885
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 29 January 2021

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ASPDAC '21
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ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2023)A Survey of Memory-Centric Energy Efficient Computer ArchitectureIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.329759534:10(2657-2670)Online publication date: Oct-2023
  • (2023)3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323675(1-9)Online publication date: 28-Oct-2023

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