Nguyen Cao Qui
ABSTRACT
Herein, we propose a fast yield estimation approach for analog circuits design in which we combine the behavioral model of circuit and the Quasi-Monte Carlo (QMC) sampling technique to accelerate yield estimation process. The behavioral model is constructed in Verilog-A based on the simulation results which are done at transistor-level; then, the accuracy of the model is verified by experimental testing on a specific analog circuit. Furthermore, instead of using random circuit samples, in this work, QMC circuit samples are adopted to obtain faster convergence rates for the yield prediction process. In conventional analog design stage, designers repeat a number of yield estimation process to select the optimal design point. Each yield estimation effort is a time-consuming process since designers have to simulate on a large number of circuits. Unlike the conventional method, in this work, we build a look-up table for constructing behavioral model of any given circuit; then, this table can be reused in repeating the yield-estimation processes. Therefore, the proposed method can significantly reduce the time for the yield estimation process. Experimental results show that the proposed approach can speed-up the yield estimation process 8 times compared to conventional simulation-based methods with a reasonable drop in accuracy (less than 5%).
- Hocevar, D., Lightner, M. and Trick, T. 1983. A study of variance reduction techniques for estimating circuit yields. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 2, 3 (Jul. 1983), 279--287. DOI= http://doi.org/10.1109/TCAD.1983.1270035.Google Scholar
Digital Library
- Jaffari, J. and Anis M. 2011. On efficient LHS-based yield analysis of analog circuits. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 30, 1 (Jan. 2011) 159-163. DOI = http://doi.org/10.1109/TCAD.2010.2070930.Google ScholarDigital Library
- Bayrakci, A., Demir A. and Tasiran S. 2011. Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 29, 9 (Sep. 2010) 1328-1341. DOI = http://doi.org/10.1109/TCAD.2010.2049042.Google ScholarDigital Library
- Singhee, A. and Rutenbar, R. 2007. From finance to flip flops: A study of fast quasi-Monte Carlo methods from computational finance applied to statistical circuit analysis. In Proceedings of the 8th International Symposium on Quality Electronic Design (San Jose, CA, USA, March 26-28, 2007). ISQED'07., New York, NY, 685--692. DOI = http://doi.org/10.1109/ISQED.2007.79.Google ScholarDigital Library
- Taddiken M., Hillebrand T., Paul S. and Peters-Drolshagen D. 2017 Variation- and degradation-aware stochastic behavioral modeling of analog circuit components. In Proceedings of the IEEE 14th Int. Conf. Synth. Modeling Anal. Simulation Methods Appl. Circuit Design (Giardini Naxos, Italy, Jun. 12--15, 2017). SMACD'17, New York, NY 1-4. DOI = http://doi.org/10.1109/SMACD.2017.7981581.Google Scholar
- Taddiken M., Paul S. and Peters-Drolshagen D. 2018. ReSeMBleD-Methods for Response Surface Model Behavioral Description. In Proceedings of the IEEE 15th Int. Conf. Synth. Modeling Anal. Simulation Methods Appl. Circuit Design (Prague, Czech Republic, July 2-5, 2018). SMACD'18., New York, NY, 157--160. DOI = http://doi.org/10.1109/SMACD.2018.8434907.Google ScholarCross Ref
- Zeng W., Zhu H., Zeng X., Zhou D., Liu R. and Li X. 2017. C-yes: An efficient parametric yield estimation approach for analog and mixed-signal circuits based on multicorner-multiperformance correlations. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 36, 6 (Sep. 2016) 899-912. DOI = http://doi.org/10.1109/TCAD.2016.2613927.Google ScholarDigital Library
- Odabasi, I.-C., Yelten, M.-B., Afacan, E., Baskaya F., Pusane, A.-E., Dundar, G. 2018. A Rare Event Based Yield Estimation Methodology for Analog Circuits. In Proceedings of the IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (Budapest, Hungary, April 25-27, 2018). DDECS'18., New York, NY, 33--38. DOI http://doi.org/10.1109/DDECS.2018.00013.Google ScholarCross Ref
- Chenming, H. et. al. 2005, Manual: BSIM4.5 MOSFET model. University of California, Berkeley, CA, USA.Google Scholar
Index Terms
- A Fast Yield Estimation Approach Considering Foundry Variation for Analog Design
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