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A Fast Yield Estimation Approach Considering Foundry Variation for Analog Design

Published: 29 May 2020 Publication History

Abstract

Herein, we propose a fast yield estimation approach for analog circuits design in which we combine the behavioral model of circuit and the Quasi-Monte Carlo (QMC) sampling technique to accelerate yield estimation process. The behavioral model is constructed in Verilog-A based on the simulation results which are done at transistor-level; then, the accuracy of the model is verified by experimental testing on a specific analog circuit. Furthermore, instead of using random circuit samples, in this work, QMC circuit samples are adopted to obtain faster convergence rates for the yield prediction process. In conventional analog design stage, designers repeat a number of yield estimation process to select the optimal design point. Each yield estimation effort is a time-consuming process since designers have to simulate on a large number of circuits. Unlike the conventional method, in this work, we build a look-up table for constructing behavioral model of any given circuit; then, this table can be reused in repeating the yield-estimation processes. Therefore, the proposed method can significantly reduce the time for the yield estimation process. Experimental results show that the proposed approach can speed-up the yield estimation process 8 times compared to conventional simulation-based methods with a reasonable drop in accuracy (less than 5%).

References

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Jaffari, J. and Anis M. 2011. On efficient LHS-based yield analysis of analog circuits. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 30, 1 (Jan. 2011) 159-163. DOI = http://doi.org/10.1109/TCAD.2010.2070930.
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Bayrakci, A., Demir A. and Tasiran S. 2011. Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation. IEEE Trans. Comput.-Aied Design Integr. Circuits Syst. 29, 9 (Sep. 2010) 1328-1341. DOI = http://doi.org/10.1109/TCAD.2010.2049042.
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Taddiken M., Hillebrand T., Paul S. and Peters-Drolshagen D. 2017 Variation- and degradation-aware stochastic behavioral modeling of analog circuit components. In Proceedings of the IEEE 14th Int. Conf. Synth. Modeling Anal. Simulation Methods Appl. Circuit Design (Giardini Naxos, Italy, Jun. 12--15, 2017). SMACD'17, New York, NY 1-4. DOI = http://doi.org/10.1109/SMACD.2017.7981581.
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  1. A Fast Yield Estimation Approach Considering Foundry Variation for Analog Design

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    ICECC '20: Proceedings of the 3rd International Conference on Electronics, Communications and Control Engineering
    April 2020
    73 pages
    ISBN:9781450374996
    DOI:10.1145/3396730
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 29 May 2020

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    Author Tags

    1. Quasi-Monte Carlo
    2. analog circuit
    3. behavioral model
    4. yield estimation

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