skip to main content
10.1145/3400302.3415605acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

Aadam: a fast, accurate, and versatile <u>a</u>ging-<u>a</u>ware cell library <u>d</u>el<u>a</u>y <u>m</u>odel using feed-forward neural network

Published: 17 December 2020 Publication History

Abstract

With the CMOS technology scaling, transistor aging has become one major issue affecting circuit reliability and lifetime. There are two major classes of existing studies that model the aging effects in the circuit delay. One is at transistor-level, which is highly accurate but very slow. The other is at gate-level, which is faster but less accurate. Moreover, most prior studies only consider a limited subset or limited value ranges of aging factors.
In this paper, we propose Aadam, a fast, accurate, and versatile aging-aware delay model for generic cell libraries. In Aadam, we first use transistor-level SPICE simulations to accurately characterize the delay degradation of each library cell under a versatile set of aging factors, including both physical parameters (i.e., initial threshold voltage and transistor width/length ratio) and operating conditions (i.e., working temperature, signal probability, input signal slew range, output load capacitance range, and projected lifetime). For each library cell, we then train a feed-forward neural network (FFNN) to learn the relation between the input aging factors and output cell delay degradation. Therefore, for a given input circuit and a given combination of aging factors, we can use the trained FFNNs to quickly and accurately infer the delay degradation for each gate in the circuit. Finally, to effectively estimate the aging-aware lifetime delay of large-scale circuits, we also integrate Aadam into a state-of-the-art static timing analysis tool called OpenTimer. Experimental results demonstrate that Aadam achieves fast estimation of the aging-induced delay with high accuracy close to transistor-level simulation.

References

[1]
M Alam, K Kang, BC Paul, and K Roy. 2007. Reliability-and process-variation aware design of vlsi circuits. In 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IEEE, 17--25.
[2]
Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, and Jörg Henkel. 2016. Reliability-aware design to suppress aging. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 1--6.
[3]
Hussam Amrouch, Javier Martin-Martinez, Victor M van Santen, Miquel Moras, Rosana Rodriguez, Montserrat Nafria, and Jörg Henkel. 2015. Connecting the physical and application level towards grasping aging effects. In 2015 IEEE International Reliability Physics Symposium. IEEE, 3D-1.
[4]
Hussam Amrouch, Victor M van Santen, Thomas Ebi, Volker Wenzel, and Jörg Henkel. 2014. Towards interdependencies of aging mechanisms. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 478--485.
[5]
W. T. Anderson. 2001. Semiconductor device reliability in extreme high temperature space environments. In 2001 IEEE Aerospace Conference Proceedings (Cat. No.01TH8542), Vol. 5. 2457--2462 vol.5.
[6]
Senthil Arasu, Mehrdad Nourani, John M Carulli, and Vijay K Reddy. 2015. Controlling aging in timing-critical paths. IEEE Design & Test 33, 4 (2015), 82--91.
[7]
Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, and Vivek De. 2003. Parameter variations and impact on circuits and microarchitecture. In Proceedings of the 40th annual Design Automation Conference. 338--342.
[8]
Léon Bottou. 1998. Online learning and stochastic approximations. On-line learning in neural networks 17, 9 (1998), 142.
[9]
F. Brglez, D. Bryan, and K. Kozminski. 1989. Combinational profiles of sequential benchmark circuits. In Circuits and Systems, 1989., IEEE International Symposium on. 1929--1934 vol.3.
[10]
F. Brglez and H. Fujiwara. 1985. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran. In Proceedings of IEEE Int'l Symposium Circuits and Systems (ISCAS 85). IEEE Press, Piscataway, N.J., 677--692.
[11]
Rakesh Chadha and J Bhasker. 2009. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer.
[12]
F. Corno, M. S. Reorda, and G. Squillero. 2000. RT-level ITC'99 benchmarks and first ATPG results. IEEE Design Test of Computers 17, 3 (July 2000), 44--53.
[13]
Balbir S Dhillon. 2000. Medical device reliability and associated areas. CRC Press.
[14]
Mojtaba Ebrahimi, Fabian Oboril, Saman Kiamehr, and Mehdi B Tahoori. 2013. Aging-aware logic synthesis. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 61--68.
[15]
Xavier Glorot and Yoshua Bengio. 2010. Understanding the difficulty of training deep feedforward neural networks. In Proceedings of the thirteenth international conference on artificial intelligence and statistics. 249--256.
[16]
Dennis Gnad, Muhammad Shafique, Florian Kriebel, Semeen Rehman, Duo Sun, and Jörg Henkel. 2015. Hayat: Harnessing dark silicon and variability for aging deceleration and balancing. In 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 1--6.
[17]
Google. 2020. Tensorflow: An end-to-end open source machine learning platform. (2020). https://www.tensorflow.org/
[18]
Marco Gori. 2018. Chapter 5 - Deep Architectures. In Machine Learning, Marco Gori (Ed.). Morgan Kaufmann, 236 -- 338. http://www.sciencedirect.com/science/article/pii/B9780081006597000051
[19]
Jörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani Nassif, Muhammad Shafique, Mehdi Tahoori, and Norbert Wehn. 2013. Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 1--10.
[20]
Ke Huang, Xinqiao Zhang, and Naghmeh Karimi. 2019. Real-Time Prediction for IC Aging Based on Machine Learning. IEEE Transactions on Instrumentation and Measurement 68, 12 (2019), 4756--4764.
[21]
Tsung-Wei Huang and Martin DF Wong. 2015. OpenTimer: A high-performance timing analysis tool. In 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 895--902.
[22]
Andrew B Kahng. 2018. New directions for learning-based IC design tools and methodologies. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 405--410.
[23]
Andrew B Kahng, Uday Mallappa, and Lawrence Saul. 2018. Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis. In 2018 IEEE 36th International Conference on Computer Design (ICCD). IEEE, 603--612.
[24]
Mehdi Kamal, Qing Xie, Massoud Pedram, Ali Afzali-Kusha, and Saeed Safari. 2012. An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits. In 2012 IEEE 30th International Conference on Computer Design (ICCD). IEEE, 352--357.
[25]
Naghmeh Karimi and Ke Huang. 2016. Prognosis of NBTI aging using a machine learning scheme. In 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE, 7--10.
[26]
Naghmeh Karimi, Arun Karthik Kanuparthi, Xueyang Wang, Ozgur Sinanoglu, and Ramesh Karri. 2015. Magic: Malicious aging in circuits/cores. ACM Transactions on Architecture and Code Optimization (TACO) 12, 1 (2015), 1--25.
[27]
John Keane and Chris H Kim. 2011. Transistor aging. IEEE Spectrum 48, 5 (2011), 28--33.
[28]
Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, and Mehdi B Tahoori. 2014. Aging-aware standard cell library design. In 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--4.
[29]
Saman Kiamehr, Farshad Firouzi, and Mehdi B Tahoori. 2013. Aging-aware timing analysis considering combined effects of NBTI and PBTI. In International Symposium on Quality Electronic Design (ISQED). IEEE, 53--59.
[30]
Dominik Lorenz, Georg Georgakos, and Ulf Schlichtmann. 2009. Aging analysis of circuit timing considering NBTI and HCI. In 2009 15th IEEE International On-Line Testing Symposium. IEEE, 3--8.
[31]
Mayler Martins, Jody Maick Matos, Renato P Ribas, André Reis, Guilherme Schlinker, Lucio Rech, and Jens Michelsen. 2015. Open cell library in 15nm FreePDK technology. In Proceedings of the 2015 Symposium on International Symposium on Physical Design. 171--178.
[32]
Spencer Millican, Yang Sun, Soham Roy, and Vishwani Agrawal. 2019. Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. In 2019 IEEE 28th Asian Test Symposium (ATS). IEEE, 13--135.
[33]
Pierre Sermanet, Soumith Chintala, and Yann LeCun. 2012. Convolutional neural networks applied to house numbers digit classification. In Proceedings of the 21st International Conference on Pattern Recognition (ICPR2012). IEEE, 3288--3291.
[34]
Robert H Tu, Elyse Rosenbaum, Wilson Y Chan, Chester C Li, Eric Minami, Khandker Quader, Ping K Ko, and Chenming Hu. 1993. Berkeley reliability tools-BERT. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, 10 (1993), 1524--1534.
[35]
Bogdan Tudor, Joddy Wang, Weidong Liu, and Hany Elhak. 2011. MOS device aging analysis with HSPICE and CustomSim. Synopsys, White Paper (2011). https://www.synopsys.com/content/dam/synopsys/verification/white-papers/mosra-wp.pdf
[36]
Bogdan Tudor, Joddy Wang, Charly Sun, Zhaoping Chen, Zhijia Liao, Robin Tan, Weidong Liu, and Frank Lee. 2010. MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45nm and below. In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. IEEE, 1645--1647.
[37]
Jyothi Bhaskarr Velamala, Venkatesa Ravi, and Yu Cao. 2011. Failure diagnosis of asymmetric aging under NBTI. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 428--433.
[38]
Arunkumar Vijayan, Krishnendu Chakrabarty, and Mehdi B Tahoori. 2019. Machine Learning-Based Aging Analysis. In Machine Learning in VLSI Computer-Aided Design. Springer, 265--289.
[39]
Arunkumar Vijayan, Abhishek Koneru, Saman Kiamehr, Krishnendu Chakrabarty, and Mehdi B Tahoori. 2016. Fine-grained aging-induced delay prediction based on the monitoring of run-time stress. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 5 (2016), 1064--1075.
[40]
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma Vrudhula, Frank Liu, and Yu Cao. 2007. The impact of NBTI on the performance of combinational and sequential circuits. In Proceedings of the 44th annual Design Automation Conference. 364--369.
[41]
Wei Zhao and Yu Cao. 2006. New generation of predictive technology model for sub-45 nm early design exploration. IEEE Transactions on Electron Devices 53, 11 (2006), 2816--2823.

Cited By

View all
  • (2025)Graph neural network based cell library characterization method for fast design technology co-optimizationIntegration10.1016/j.vlsi.2024.102316101(102316)Online publication date: Mar-2025
  • (2024)The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode MechanismsMicromachines10.3390/mi1501012715:1(127)Online publication date: 12-Jan-2024
  • (2024)Multi-View Graph Learning for Path-Level Aging-Aware Timing PredictionElectronics10.3390/electronics1317347913:17(3479)Online publication date: 2-Sep-2024
  • Show More Cited By
  1. Aadam: a fast, accurate, and versatile aging-aware cell library delay model using feed-forward neural network

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design
    November 2020
    1396 pages
    ISBN:9781450380263
    DOI:10.1145/3400302
    • General Chair:
    • Yuan Xie
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    In-Cooperation

    • IEEE CAS
    • IEEE CEDA
    • IEEE CS

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 17 December 2020

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. aging
    2. cell library
    3. delay model
    4. machine learning
    5. reliability

    Qualifiers

    • Research-article

    Conference

    ICCAD '20
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 457 of 1,762 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)29
    • Downloads (Last 6 weeks)7
    Reflects downloads up to 06 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2025)Graph neural network based cell library characterization method for fast design technology co-optimizationIntegration10.1016/j.vlsi.2024.102316101(102316)Online publication date: Mar-2025
    • (2024)The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode MechanismsMicromachines10.3390/mi1501012715:1(127)Online publication date: 12-Jan-2024
    • (2024)Multi-View Graph Learning for Path-Level Aging-Aware Timing PredictionElectronics10.3390/electronics1317347913:17(3479)Online publication date: 2-Sep-2024
    • (2024)Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active LearningProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685965(1-7)Online publication date: 9-Sep-2024
    • (2024)Fast and Accurate Aging-Aware Cell Timing Model via Graph LearningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.329891771:1(156-160)Online publication date: Jan-2024
    • (2024)Re-GNN: A New Model for Predicting Circuit Reliability DegradationData Science10.1007/978-981-97-8743-2_21(269-280)Online publication date: 31-Oct-2024
    • (2023)Machine Learning in EDA: When and How2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299822(1-6)Online publication date: 10-Sep-2023
    • (2023)Lightning Talk: All Routes to Timing Closure2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247801(1-2)Online publication date: 9-Jul-2023
    • (2022)Gate Sizing-Based Lifetime Reliability Improvement of Integrated CircuitsLifetime Reliability-aware Design of Integrated Circuits10.1007/978-3-031-15345-7_4(51-64)Online publication date: 17-Nov-2022

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media