research-article

Dual-output LUT merging during FPGA technology mapping

Authors:

Guojie LuoAuthors Info & Claims

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Article No.: 132, Pages 1 - 9

https://doi.org/10.1145/3400302.3415617

Published: 17 December 2020 Publication History

Abstract

Modern commercial Field-Programmable Gate Array (FPGA) architectures support dual-output look-up tables (LUTs). If the number of total inputs in two small LUTs do not exceed the constraint, e.g., 5 in Xilinx UltraScale+ series, we can pack them into one dual-output LUT to reduce area, i.e., the number of LUTs. However, previous works have not fully utilized this feature. They usually generate single-output LUTs in the technology mapping phase and merge LUTs in a later packing phase. In this situation, they cannot get LUT merging information during technology mapping and will generate some single-output LUTs that are not suitable for merging.

In this work, we directly generate dual-output LUTs in the technology mapping phase and propose a novel cut-based mapping flow. The mapping flow consists of several mapping passes with different cut selection metrics. In each pass, we first compute the priority single-output cuts of each node. Then, we merge dual-output cuts from the priority cuts to generate a mapped LUT netlist. Finally, we do some local refinement to further improve the merging rate and reduce area. Experimental evaluation shows that our mapping flow can merge up to 14.89% more LUTs and save up to 13.98% area on average, compared to the state-of-the-art technology mapping tool ABC, without worsening the total delay.

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Cited By

Calvino ADe Micheli G(2023)Technology Mapping Using Multi-Output Library Cells2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323999(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323999
Raj KBodapati S(2022)FPGA Based Light Weight Encryption of Medical Data for IoMT Devices using ASCON Cipher2022 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES54909.2022.00048(196-201)Online publication date: Dec-2022
https://doi.org/10.1109/iSES54909.2022.00048

Index Terms

Dual-output LUT merging during FPGA technology mapping
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
      2. Technology-mapping

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cover image ACM Conferences

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

November 2020

1396 pages

ISBN:9781450380263

DOI:10.1145/3400302

General Chair:
Yuan Xie
Univ. of California, Santa Barbara, CA

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 17 December 2020

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Beijing Academy of Artificial Intelligence (BAAI)
Key Area R&D Program of Guangdong Province
Beijing Municipal Science and Technology Program

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ICCAD '20

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SIGDA

ICCAD '20: IEEE/ACM International Conference on Computer-Aided Design

November 2 - 5, 2020

Virtual Event, USA

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Cited By

Calvino ADe Micheli G(2023)Technology Mapping Using Multi-Output Library Cells2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323999(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323999
Raj KBodapati S(2022)FPGA Based Light Weight Encryption of Medical Data for IoMT Devices using ASCON Cipher2022 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES54909.2022.00048(196-201)Online publication date: Dec-2022
https://doi.org/10.1109/iSES54909.2022.00048

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