skip to main content
10.1145/3400302.3415694acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

A quantitative defense framework against power attacks on multi-tenant FPGA

Published: 17 December 2020 Publication History

Abstract

The development and application of various Machine Learning algorithms demand high computing capabilities. As a result, field-programmable gate arrays (FPGAs) are being used as hardware accelerators, and more recently deployed in cloud servers by leading vendors to provide reconfigurable computing capabilities. Although such cloud-FPGA platform is bringing significant performance benefits, it also creates a unique attack surface where the hardware resources of an FPGA are shared by multiple users. Power attack targeting the power distribution network (PDN) is among the most threatening ones against multi-tenant FPGAs. In such attack, the malicious users leverage power plundering circuits to manipulate the PDN and cause a voltage drop, thus injecting timing faults to the victim applications. Besides, since most cloud-FPGAs are being used for computing-intensive tasks that consume a large amount of power, therefore, typical FPGA applications may still encounter timing faults even without power attacks. Unlike power attacks, we classify this problem as a reliability issue.
To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop.

References

[1]
2014. Altera and IBM Unveil FPGA-Accelerated POWER Systems. https://www.hpcwire.com/off-the-wire/altera-ibm-unveil-fpga-accelerated-power-systems/
[2]
2014. Vivado timing closure physical optimization. https://www.xilinx.com/video/hardware/vivado-timing-closure-physical-optimization.html
[3]
2016. AES-128 Encryption. https://opencores.org/projects/aes-128_pipelined_encryption
[4]
2016. Here's what an Intel Broadwell Xeon with a built-in FPGA looks like. https://www.theregister.co.uk/2016/03/14/intel_xeon_fpga/
[5]
2018. MD5 Pipelined. https://opencores.org/projects/md5_pipelined
[6]
2018. SHA cores. https://opencores.org/projects/sha_core
[7]
2019. double fpu verilog. https://opencores.org/projects/double_fpu
[8]
Md Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark Tehranipoor, and Domenic Forte. 2019. Ram-jam: Remote temperature and voltage fault attack on fpgas using memory collisions. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). IEEE, 48--55.
[9]
C. Albrecht. 2005. IWLS 2005 Benchmarks. Technical Report.
[10]
Arnab Bag, Sikhar Patranabis, Debapriya Basu Roy, and Debdeep Mukhopadhyay. 2018. Cryptographically secure multi-tenant provisioning of FPGAs. arXiv preprint arXiv:1802.04136 (2018).
[11]
J-L Danger, Sylvain Guilley, and Philippe Hoogvorst. 2009. High speed true random number generator based on open loop structures in FPGAs. Microelectronics journal 40, 11 (2009), 1650--1656.
[12]
Rana Elnaggar, Ramesh Karri, and Krishnendu Chakrabarty. 2019. Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 7--12.
[13]
Viktor Fischer, Florent Bernard, Nathalie Bochard, and Michal Varchola. 2008. Enhancing security of ring oscillator-based trng implemented in FPGA. In 2008 International Conference on Field Programmable Logic and Applications. IEEE, 245--250.
[14]
Ilias Giechaskiel, Kasper B Rasmussen, and Ken Eguro. 2018. Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires. In Proceedings of the 2018 on Asia Conference on Computer and Communications Security. ACM, 15--27.
[15]
Dennis RE Gnad, Fabian Oboril, and Mehdi B Tahoori. 2017. Voltage drop-based fault attacks on FPGAs using valid bitstreams. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1--7.
[16]
Ahmed Khawaja, Joshua Landgraf, Rohith Prakash, Michael Wei, Eric Schkufza, and Christopher J Rossbach. 2018. Sharing, protection, and compatibility for reconfigurable fabric with amorphos. In 13th {USENIX} Symposium on Operating Systems Design and Implementation ({OSDI} 18). 107--127.
[17]
Jonas Krautter, Dennis RE Gnad, and Mehdi B Tahoori. 2018. FPGAhammer: remote voltage fault attacks on shared FPGAs, suitable for DFA on AES. IACR Transactions on Cryptographic Hardware and Embedded Systems (2018), 44--68.
[18]
Yukui Luo and Xiaolin Xu. 2019. HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires. In 2019 International Conference on Field-Programmable Technology (ICFPT). IEEE, 331--334.
[19]
Yukui Luo and Xiaolin Xu. 2020. A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 210--210.
[20]
Dina Mahmoud and Mirjana Stojilović. 2019. Timing Violation Induced Faults in Multi-Tenant FPGAs. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1745--1750.
[21]
Abhranil Maiti, Jeff Casarona, Luke McHale, and Patrick Schaumont. 2010. A large scale characterization of RO-PUF. In 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). IEEE, 94--99.
[22]
Abhranil Maiti and Patrick Schaumont. 2011. Improved ring oscillator PUF: An FPGA-friendly secure primitive. Journal of cryptology 24, 2 (2011), 375--397.
[23]
Kit Murdock, David Oswald, Flavio D Garcia, Jo Van Bulck, Daniel Gruss, and Frank Piessens. 2020. Plundervolt: Software-based fault injection attacks against Intel SGX. In 2020 IEEE Symposium on Security and Privacy (SP).
[24]
George Provelengios, Daniel Holcomb, and Russell Tessier. 2019. Characterizing Power Distribution Attacks in Multi-User FPGA Environments. In 2019 International Conference on Field-Programmable Logic and Applications (FPL). IEEE.
[25]
Pengfei Qiu, Dongsheng Wang, Yongqiang Lyu, and Gang Qu. 2019. VoltJockey: Breaching TrustZone by Software-Controlled Voltage Manipulation over Multicore Frequencies. In Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security. ACM, 195--209.
[26]
Chethan Ramesh, Shivukumar B Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel Holcomb, and Russell Tessier. 2018. FPGA side channel attacks without physical access. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 45--52.
[27]
Zane Weissman, Thore Tiemann, Daniel Moghimi, Evan Custodio, Thomas Eisenbarth, and Berk Sunar. 2019. JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arXiv preprint arXiv:1912.11523 (2019).
[28]
Knut Wold and Chik How Tan. 2009. Analysis and enhancement of random number generator in FPGA based on oscillator rings. International Journal of Reconfigurable Computing 2009 (2009), 4.
[29]
Xilinx, Inc 2017. Vivado Design Suite user Guide Partial Reconfiguration (UG909). Xilinx, Inc.
[30]
Xilinx, Inc 2018. 7 Series FPGAs Clocking Resources (UG472). Xilinx, Inc.
[31]
Xilinx, Inc 2019. Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182). Xilinx, Inc.
[32]
Xilinx, Inc 2019. MMCM and PLL Dynamic Reconfiguration (XAPP888). Xilinx, Inc.
[33]
Xin Xin, Jens-Peter Kaps, and Kris Gaj. 2011. A configurable ring-oscillator-based PUF for Xilinx FPGAs. In 2011 14th Euromicro Conference on Digital System Design. IEEE, 651--657.
[34]
Sadegh Yazdanshenas and Vaughn Betz. 2019. The Costs of Confidentiality in Virtualized FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2019).
[35]
Mark Zhao and G Edward Suh. 2018. FPGA-based remote power side-channel attacks. In 2018 IEEE Symposium on Security and Privacy (SP). IEEE, 229--244.

Cited By

View all
  • (2024)Covert-channels in FPGA-enabled SmartSSDsACM Transactions on Reconfigurable Technology and Systems10.1145/363531217:2(1-23)Online publication date: 30-Apr-2024
  • (2024)On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)ACM Transactions on Reconfigurable Technology and Systems10.1145/363320417:2(1-28)Online publication date: 30-Apr-2024
  • (2024)Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00080(443-448)Online publication date: 6-Jan-2024
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design
November 2020
1396 pages
ISBN:9781450380263
DOI:10.1145/3400302
  • General Chair:
  • Yuan Xie
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

  • IEEE CAS
  • IEEE CEDA
  • IEEE CS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 December 2020

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

ICCAD '20
Sponsor:

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)35
  • Downloads (Last 6 weeks)3
Reflects downloads up to 15 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2024)Covert-channels in FPGA-enabled SmartSSDsACM Transactions on Reconfigurable Technology and Systems10.1145/363531217:2(1-23)Online publication date: 30-Apr-2024
  • (2024)On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)ACM Transactions on Reconfigurable Technology and Systems10.1145/363320417:2(1-28)Online publication date: 30-Apr-2024
  • (2024)Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00080(443-448)Online publication date: 6-Jan-2024
  • (2024)Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure2024 27th Euromicro Conference on Digital System Design (DSD)10.1109/DSD64264.2024.00055(361-368)Online publication date: 28-Aug-2024
  • (2024)A Systematic Literature Review on Vulnerabilities, Mitigation Techniques, and Attacks in Field-Programmable Gate ArraysArabian Journal for Science and Engineering10.1007/s13369-024-09562-wOnline publication date: 23-Sep-2024
  • (2023)Fault Recovery from Multi-Tenant FPGA Voltage AttacksProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590246(557-562)Online publication date: 5-Jun-2023
  • (2023)FPGANeedleProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3568352(358-364)Online publication date: 16-Jan-2023
  • (2023)A Visionary Look at the Security of Reconfigurable Cloud ComputingProceedings of the IEEE10.1109/JPROC.2023.3330729111:12(1548-1571)Online publication date: Dec-2023
  • (2023)Introduction to Physical Layer Security and Hardware Supply Chain Security: EM Tricks to Keep Your Information and Devices Safe2023 International Symposium on Electromagnetic Compatibility – EMC Europe10.1109/EMCEurope57790.2023.10274206(1-6)Online publication date: 4-Sep-2023
  • (2023)Cross-board Power-Based FPGA, CPU, and GPU Covert ChannelsSecurity of FPGA-Accelerated Cloud Computing Environments10.1007/978-3-031-45395-3_7(173-202)Online publication date: 18-Sep-2023
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media