ABSTRACT
Optical proximity correction (OPC) for advanced technology node now has become extremely expensive and challenging. Conventional model-based OPC encounters performance degradation and large process variation, while aggressive approach such as inverse lithography technology (ILT) suffers from large computational overhead for both mask optimization and mask writing processes. In this paper, we developed Neural-ILT, an end-to-end learning-based OPC framework, which literally conducts mask prediction and ILT correction for a given layout in a single neural network, with the objectives of (1) mask printability enhancement, (2) mask complexity optimization and (3) flow acceleration. Quantitative results show that, comparing to the state-of-the-art (SOTA) learning-based OPC solution and conventional ILT flow, Neural-ILT can achieve 30× ~ 70× turn around time (TAT) speedup with lower mask complexity and comparable mask printability. We believe this work could arouse the interests of bridging well-developed deep learning toolkits to GPU-based high-performance lithographic computations to achieve groundbreaking performance boosting on various computational lithography-related tasks.
- H. Yang, W. Zhong, Y. Ma, H. Geng, R. Chen, W. Chen, and B. Yu, "VLSI mask optimization: From shallow to deep learning," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2020, pp. 434--439.Google Scholar
- J. Kuang, W.-K. Chow, and E. F. Y. Young, "A robust approach for process variation aware mask optimization," in IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), 2015, pp. 1591--1594.Google ScholarDigital Library
- Y.-H. Su, Y.-C. Huang, L.-C. Tsai, Y.-W. Chang, and S. Banerjee, "Fast lithographic mask optimization considering process variation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 8, pp. 1345--1357, 2016.Google ScholarDigital Library
- F. Liu and X. Shi, "An efficient mask optimization method based on homotopy continuation technique," in IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), 2011, pp. 1--6.Google Scholar
- J.-R. Gao, X. Xu, B. Yu, and D. Z. Pan, "MOSAIC: Mask optimizing solution with process window aware inverse correction," in ACM/IEEE Design Automation Conference (DAC), 2014, pp. 52:1--52:6.Google Scholar
- K. Hooker, B. Kuechler, A. Kazarian, G. Xiao, and K. Lucas, "ILT optimization of EUV masks for sub-7nm lithography," in Proceedings of SPIE, vol. 10446, 2017.Google Scholar
- Y. Ma, J.-R. Gao, J. Kuang, J. Miao, and B. Yu, "A unified framework for simultaneous layout decomposition and mask optimization," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, pp. 81--88.Google Scholar
- R. Pearman, J. Ungar, N. Shirali, A. Shendre, M. Niewczas, L. Pang, and A. Fujimura, "How curvilinear mask patterning will enhance the EUV process window: a study using rigorous wafer+ mask dual simulation," in Proceedings of SPIE, vol. 11178, 2019.Google Scholar
- I. Torunoglu, A. Karakas, E. Elsen, C. Andrus, B. Bremen, B. Dimitrov, and J. Ungar, "A GPU-based full-chip inverse lithography solution for random patterns," in Proceedings of SPIE, 2010, p. 764115.Google ScholarCross Ref
- V. Domnenko, B. Küchler, W. Hoppe, J. Preuninger, U. Klostermann, W. Demmerle, M. Bohn, D. Krüger, R. R. H. Kim, and L. E. Tan, "EUV computational lithography using accelerated topographic mask simulation," in Proceedings of SPIE, 2019.Google Scholar
- J. Kuang and E. F. Young, "An efficient layout decomposition approach for triple patterning lithography," in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 2013, pp. 1--6.Google Scholar
- J. Kuang, J. Ye, and E. F. Y. Young, "Simultaneous template optimization and mask assignment for DSA with multiple patterning," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2016, pp. 75--82.Google Scholar
- W. Ye, M. B. Alawieh, Y. Lin, and D. Z. Pan, "LithoGAN: End-to-end lithography modeling with generative adversarial networks," in ACM/IEEE Design Automation Conference (DAC), 2019, pp. 107:1--107:6.Google Scholar
- Y. Lin, M. Li, Y. Watanabe, T. Kimura, T. Matsunawa, S. Nojima, and D. Z. Pan, "Data efficient lithography modeling with transfer learning and active data selection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.Google ScholarDigital Library
- D. Ding, B. Yu, J. Ghosh, and D. Z. Pan, "EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2012, pp. 263--270.Google Scholar
- H. Yang, J. Su, Y. Zou, Y. Ma, B. Yu, and E. F. Y. Young, "Layout hotspot detection with feature tensor generation and deep biased learning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 6, pp. 1175--1187, 2019.Google ScholarDigital Library
- R. Chen, W. Zhong, H. Yang, H. Geng, X. Zeng, and B. Yu, "Faster region-based hotspot detection," in ACM/IEEE Design Automation Conference (DAC), 2019, pp. 146:1--146:6.Google Scholar
- X. Ma, S. Jiang, J. Wang, B. Wu, Z. Song, and Y. Li, "A fast and manufacture-friendly optical proximity correction based on machine learning," Microelectronic Engineering, vol. 168, pp. 15--26, 2017.Google ScholarCross Ref
- H. Yang, S. Li, Y. Ma, B. Yu, and E. F. Young, "GAN-OPC: Mask optimization with lithography-guided generative adversarial nets," in ACM/IEEE Design Automation Conference (DAC), 2018, pp. 131:1--131:6.Google Scholar
- B. Jiang, H. Zhang, J. Yang, and E. F. Young, "A fast machine learning-based mask printability predictor for OPC acceleration," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2019, pp. 412--419.Google Scholar
- T. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, "Benchmarking of mask fracturing heuristics," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, pp. 170--183, 2017.Google ScholarDigital Library
- H. Hopkins, "The concept of partial coherence in optics," in Proceedings of the Royal Society of London A: Mathematical, Physical and Engineering Sciences, vol. 208, no. 1093. The Royal Society, 1951, pp. 263--277.Google Scholar
- S. Banerjee, Z. Li, and S. R. Nassif, "ICCAD-2013 CAD contest in mask optimization and benchmark suite," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp. 271--274.Google Scholar
- O. Ronneberger, P. Fischer, and T. Brox, "U-net: Convolutional networks for biomedical image segmentation," in Proc. MICCAI, 2015, pp. 234--241.Google ScholarCross Ref
- W. Lv, S. Liu, Q. Xia, X. Wu, Y. Shen, and E. Y. Lam, "Level-set-based inverse lithography for mask synthesis using the conjugate gradient and an optimal time step," JVSTB, vol. 31, p. 041605, 2013.Google Scholar
- B. Jiang, X. Zhang, R. Chen, G. Chen, P. Tu, W. Li, E. F. Young, and B. Yu, "Fit: Fill insertion considering timing," in ACM/IEEE Design Automation Conference (DAC), 2019, p. 221.Google Scholar
- M.-Y. Liu, T. Breuel, and J. Kautz, "Unsupervised image-to-image translation networks," in Advances in neural information processing systems, 2017, pp. 700--708.Google Scholar
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