ABSTRACT
In recent years, 2.5D chiplet package designs have gained popularity in system integration of heterogeneous technologies. Currently, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach does not consider any package layers during extraction and optimization, and an accurate chiplet-package extraction can not be applied to heterogeneous designs without fundamental changes in standard CAD tools. In this paper, we present our Holistic and In-Context chiplet-package co-design flows for high-performance high-density 2.5D systems using standard ASIC CAD tools with zero overhead on IO pipeline depth. Our flow encompasses 2.5D-aware partitioning, chiplet-package co-planning, in-context extraction, iterative optimization, and post-design analysis and verification of the entire 2.5D system. We design our package planner with a routing and pin-planning strategy to minimize package routing congestion and timing overhead. An ARM Cortex-M0-based microcontroller system is designed as the benchmark. The performance gap to the reference 2D design reduces by 62.5% when chip-package interactions are taken into account in the holistic flow. Our in-context extraction achieves only 0.71% and 0.79% error on ground and coupling capacitance on a homogeneous system. Further, we implement a heterogeneous 2.5D system to demonstrate our novel in-context design and optimization methodology.
- M. Brunnbauer, T. Meyer, G. Ofner, K. Mueller, and R. Hagen. 2008. Embedded Wafer Level Ball Grid Array (eWLB). In International Electronics Manufacturing Technology Conference. 1--6. Google ScholarCross Ref
- Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, and Mehedi Sarwar. 2016. OpenRAM: An Open-source Memory Compiler. In International Conference on Computer-Aided Design. 93:1--93:6. Google ScholarDigital Library
- Jia-Wei Fang and Yao-Wen Chang. 2008. Area-I/O flip-chip routing for chip-package co-design. In International Conference on Computer-Aided Design. 518--522. Google ScholarCross Ref
- MD Arafat Kabir and Yarui Peng. 2020. Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. In Asia and South Pacific Design Automation Conference. 351--356. Google ScholarDigital Library
- W. Ki, W. Lee, I. MoK, I. Lee, W. Do, M. Kolbehdari, A. Copia, S. Jayaraman, C. Zwenger, and K. Lee. 2018. Chip Stackable, Ultra-thin, High-Flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-Integrated Advanced 3D WL-SiP. In IEEE Electronic Components and Technology Conference. 580--586. Google ScholarCross Ref
- Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya, Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, and Sung Kyu Lim. 2019. Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. In Design Automation Conference. 178:1--178:6. Google ScholarDigital Library
- W. Liu, Min-Sheng Chang, and T. Wang. 2014. Floorplanning and signal assignment for silicon interposer-based 3D ICs. In Design Automation Conference. 1--6. Google ScholarDigital Library
- J. Minz and S. K. Lim. 2006. Block-level 3-D Global Routing With an Application to 3-D Packaging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 10 (Oct 2006), 2248--2257. Google ScholarDigital Library
- J. R. Minz and Sung Kyu Lim. 2004. A global router for system-on-package targeting layer and crosstalk minimization. In Electrical Performance of Electronic Packaging. 99--102. Google ScholarCross Ref
- Y. Peng, T. Song, D. Petranovic, and S. K. Lim. 2017. Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs. IEEE Transactions on Components and Packaging and Manufacturing Technology 7, 6 (June 2017), 912--924. Google ScholarCross Ref
- H. Pu, H. J. Kuo, C. S. Liu, and D. C. H. Yu. 2018. A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO Packaging. In IEEE Electronic Components and Technology Conference. 45--51. Google ScholarCross Ref
- C. Tseng, C. Liu, C. Wu, and D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE Electronic Components and Technology Conference. 1--6. Google ScholarCross Ref
- Y. Xie, C. Bao, Y. Liu, and A. Srivastava. 2016. 2.5D/3D Integration Technologies for Circuit Obfuscation. In International Workshop on Microprocessor and SOC Test and Verification. 39--44. Google ScholarCross Ref
- Y. Xie, C. Bao, and A. Srivastava. 2017. Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy. Computer 50, 5 (May 2017), 62--71. Google ScholarDigital Library
- Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design
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