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Applying Multiple Level Cell to Non-volatile FPGAs

Published: 12 July 2020 Publication History

Abstract

Static random access memory– (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLCs) has not been fully exploited yet.
In this article, we study architecture of MLC-based NVFPGAs, and propose five cluster structures. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Based on explorations of the characteristics of MLC-based NVFPGAs, we further present MLC-aware timing-driven packing method to improve delay. In critical paths, our proposed method reduces the overhead of the additional delay in slow MLC cells. Experiments show that, compared to SRAM-based FPGAs, the proposed architecture with the proposed CAD flow can reduce the area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.

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  • (2025)CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341904844:1(144-156)Online publication date: 1-Jan-2025
  • (2024)Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546880(1-6)Online publication date: 25-Mar-2024
  • (2024)Implementing Neural Networks on Nonvolatile FPGAs With ReprogrammingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344370843:11(3961-3972)Online publication date: 1-Nov-2024
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      Published In

      cover image ACM Transactions on Embedded Computing Systems
      ACM Transactions on Embedded Computing Systems  Volume 19, Issue 4
      July 2020
      196 pages
      ISSN:1539-9087
      EISSN:1558-3465
      DOI:10.1145/3407675
      • Editor:
      • Tulika Mitra
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 12 July 2020
      Accepted: 01 May 2020
      Revised: 01 March 2020
      Received: 01 May 2019
      Published in TECS Volume 19, Issue 4

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      Author Tags

      1. CAD flow
      2. FPGA
      3. multiple level cell
      4. non-volatile memory

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      • Research-article
      • Research
      • Refereed

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      • Research and Application of Key Technology for Intelligent Dispatching and Security Early-warning of Large Power Grid
      • State Grid Corporation of China
      • National Key R8D Program of China

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      View all
      • (2025)CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341904844:1(144-156)Online publication date: 1-Jan-2025
      • (2024)Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546880(1-6)Online publication date: 25-Mar-2024
      • (2024)Implementing Neural Networks on Nonvolatile FPGAs With ReprogrammingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344370843:11(3961-3972)Online publication date: 1-Nov-2024
      • (2023)Correlation-guided Placement for Nonvolatile FPGAs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247963(1-6)Online publication date: 9-Jul-2023
      • (2022)Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319768541:11(3591-3601)Online publication date: 1-Nov-2022
      • (2022)SSRL: Single Skyrmion Reconfigurable Logic Utilizing 2-D Magnus Force on Magnetic RacetracksIEEE Journal on Exploratory Solid-State Computational Devices and Circuits10.1109/JXCDC.2023.32380308:2(203-211)Online publication date: Dec-2022
      • (2022)Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAsJournal of Systems Architecture10.1016/j.sysarc.2022.102532128(102532)Online publication date: Jul-2022

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