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Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits

Published: 22 October 2020 Publication History

Abstract

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10−19J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

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Cited By

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  • (2024)Superconductive Electronics: A 25-Year Review [Feature]IEEE Circuits and Systems Magazine10.1109/MCAS.2024.337649224:2(16-33)Online publication date: Oct-2025
  • (2024)Towards Multiphase Clocking in Single-Flux Quantum Systems2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473879(582-587)Online publication date: 22-Jan-2024
  • (2023)Synthesis of SFQ Circuits with Compound Gates2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321853(1-6)Online publication date: 16-Oct-2023
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  1. Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits

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    Published In

    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 17, Issue 1
    January 2021
    232 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/3425108
    • Editor:
    • Ramesh Karri
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 22 October 2020
    Accepted: 01 July 2020
    Revised: 01 June 2020
    Received: 01 November 2019
    Published in JETC Volume 17, Issue 1

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    Author Tags

    1. AIG
    2. DAG
    3. RSFQ
    4. SDE
    5. SFQ
    6. directed acyclic graph
    7. dual clocking method
    8. energy-efficient
    9. graph
    10. graph partitioning
    11. logic synthesis
    12. low-power
    13. macro clock
    14. micro clock
    15. path balancing
    16. superconducting digital electronics
    17. superconducting single flux quantum
    18. technology mapping

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    • Research-article
    • Research
    • Refereed

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    • Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office
    • Software and Hardware Foundations program of the National Science Foundation

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    Cited By

    View all
    • (2024)Superconductive Electronics: A 25-Year Review [Feature]IEEE Circuits and Systems Magazine10.1109/MCAS.2024.337649224:2(16-33)Online publication date: Oct-2025
    • (2024)Towards Multiphase Clocking in Single-Flux Quantum Systems2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473879(582-587)Online publication date: 22-Jan-2024
    • (2023)Synthesis of SFQ Circuits with Compound Gates2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321853(1-6)Online publication date: 16-Oct-2023
    • (2022)Superconducting single flux quantum (SFQ) technology for power-efficiency computingCCF Transactions on High Performance Computing10.1007/s42514-022-00114-y4:2(182-210)Online publication date: 21-Jul-2022
    • (2022)A survey on superconducting computing technology: circuits, architectures and design toolsCCF Transactions on High Performance Computing10.1007/s42514-022-00089-w4:1(1-22)Online publication date: 16-Mar-2022

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