research-article

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip

Authors:

Zhongsheng Chen,

Jianhui JiangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 1

Article No.: 8, Pages 1 - 26

https://doi.org/10.1145/3414060

Published: 27 October 2020 Publication History

Abstract

Very-large-scale network-on-chip (VLS-NoC) has become a promising fabric for supercomputers, but this fabric may encounter the many-fault problem. This article proposes a deterministic routing algorithm to tolerate the effects of many faults in VLS-NoCs. This approach generates routing tables offline using a breadth-first traversal algorithm and stores a routing table locally in each switch for online packet transmission. The approach applies the Tarjan algorithm to degrade the faulty NoC and maximizes the number of available nodes in the reconfigured NoC. In 2D NoCs, the approach updates routing tables of some nodes using the deprecated channel/node rules and avoids deadlocks in the NoC. In 3D NoCs, the approach uses a forbidden-turn selection algorithm and detour rules to prevent faceted rings and ensures the NoC is deadlock-free. Experimental results demonstrate that the proposed approach provides fault-free communications of 2D and 3D NoCs after injecting 40 faulty links. Meanwhile, it maximizes the number of available nodes in the reconfigured NoC. The approach also outperforms existing algorithms in terms of average latency, throughput, and energy consumption.

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Bhattacharjee SSarkar SDas KSadhu ASarkar B(2025)Utilization of Two Cross Two Switch for Bitonic Sorting CircuitMicro and Nanosystems10.2174/011876402931491524082817021717:1(45-57)Online publication date: Jan-2025
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Xu DOuyang YZhou WHuang ZLiang HWen X(2023)RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional ChannelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332159831:12(2061-2074)Online publication date: 1-Dec-2023
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Zhuang HLi XChang JWang D(2023)An Efficient Algorithm for Hamiltonian Path Embedding of $k$-Ary $n$-Cubes under the Partitioned Edge Fault ModelIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.3264698(1-14)Online publication date: 2023
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Index Terms

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Fault-tolerant network topologies
2. Hardware
  1. Robustness
    1. Fault tolerance
      1. System-level fault tolerance
  2. Very large scale integration design
    1. Design reuse and communication-based design
      1. Network on chip

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 1

January 2021

234 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3422280

Editor:
X. Sharon Hu
University of Notre Dame, USA

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Copyright © 2020 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 October 2020

Accepted: 01 July 2020

Revised: 01 July 2020

Received: 01 March 2020

Published in TODAES Volume 26, Issue 1

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Cited By

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https://doi.org/10.2174/0118764029314915240828170217
Xu DOuyang YZhou WHuang ZLiang HWen X(2023)RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional ChannelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332159831:12(2061-2074)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3321598
Zhuang HLi XChang JWang D(2023)An Efficient Algorithm for Hamiltonian Path Embedding of $k$-Ary $n$-Cubes under the Partitioned Edge Fault ModelIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.3264698(1-14)Online publication date: 2023
https://doi.org/10.1109/TPDS.2023.3264698
Bhowmik BN G(2023)Design of a Fault-Tolerant Pseudo-3D Routing2023 IEEE International Test Conference India (ITC India)10.1109/ITCIndia59034.2023.10235563(1-6)Online publication date: 23-Jul-2023
https://doi.org/10.1109/ITCIndia59034.2023.10235563
Li JQin CSun X(2023)An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoCMicroelectronics Journal10.1016/j.mejo.2023.105989142(105989)Online publication date: Dec-2023
https://doi.org/10.1016/j.mejo.2023.105989
Zhang YJi PZhu PPeng ZLi HJiang J(2023)Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-ChipJournal of Computer Science and Technology10.1007/s11390-022-2553-338:2(405-421)Online publication date: 30-Mar-2023
https://doi.org/10.1007/s11390-022-2553-3
Ge MNi XQi XChen SHuang JKang YWu F(2022)Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chipsACM Transactions on Design Automation of Electronic Systems10.1145/348096127:1(1-30)Online publication date: 31-Jan-2022
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