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Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited)
We are living in a connected world with access to data in vast amounts. This connectivity is enhanced by more intelligent sensors and human-computer interfaces bringing people closer to computation in a more natural and accessible way. Instant data ...
Communication architecture enabling 100x accelerated simulation of biological neural networks
To further develop the understanding of cognitive processes in the human cortex, neuroscientists seek to simulate relevant biological neural networks in the order of 109 neurons with natural densities of 104 synapses per neuron. To observe long-term ...
Pathfinding for 2.5D interconnect technologies
As conventional technology scaling becomes harder, 2.5D integration provides a viable pathway to building larger systems at lower cost. Therefore recently, there has been a proliferation of multiple 2.5D integration technologies that offer different ...
Global interconnects in VLSI complexity single flux quantum systems
On-chip signal routing has become an issue of growing importance in modern VLSI complexity single flux quantum (SFQ) systems. In this paper, different routing methods for these systems are described. The routing methods include either passive ...
Building a quantum computer (invited)
Quantum computing has leapt from concept to commercial enterprise in four decades and now the complexities of computer hardware apply to quantum computing but with the added challenge that computer fundamentals are radically different.
Extending quantum systems with optical interconnects (invited)
As quantum systems scale, the challenge of connecting qubits with high fidelity communication links looms large. In the short term, traditional VLSI packaging technologies are being adapted to the unique material constraints of the various qubit ...
Wafer scale interconnect and pathfinding for machine learning hardware (invited)
The extreme compute requirements of Machine Learning (ML) drives an entirely new generation of hardware. The very compute-intensive ML training is generally done in data centers using re-purposed GPUs. This provides cost-efficient floating-point compute ...
Analytical modeling of NoCs for fast simulation and design exploration (invited)
Networks-On-Chip are widely used in modern System-on-Chips to provide necessary communication between growing number of IP blocks. They are paramount to performance and power as they constitute primary shared resources in the systems. Modern system-...
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited)
DSAs for machine learning (ML) such as Google TPU, Microsoft Brainwave, Xilinx xDNN are becoming prominent because of high energy-efficiency and performance. These DSAs perform dense linear algebra efficiently by minimizing data movement, exploiting ...
Revisiting inherent noise floors for interconnect prediction
Today's synthesis, placement and routing (SP&R) tools routinely handle millions of instances. Accurate prediction of outcomes is needed to avoid long wasted runtimes from, e.g., unroutable floor-plans or placements. However, tool outputs have inherent ...
3D NoC emulation model on a single FPGA
Networks-on-Chip (NoCs) have emerged as a promising solution for the communication crisis in large and highly interconnected Systems-on-Chip. To allow investigating path finding solutions for NoC architectures and provide useful insights into the ...
Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power
Static Random-Access Memory (SRAM) is a key component of modern systems-on-chip (SOCs), appearing in on-chip cache memories, FIFOs, and register files. Increasingly, modern SOCs embed more memory hierarchies and various modules which require on-chip ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
SLIP '18 | 8 | 6 | 75% |
Overall | 8 | 6 | 75% |