skip to main content
research-article

SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling

Published: 23 October 2020 Publication History

Abstract

Detailed routing is one of the most time-consuming steps of physical synthesis of integrated circuits. Also, it is very challenging due to the complexity of the design rules that the router must obey. In this article, we present SmartDR, a detailed routing system that focuses on good design rule handling and fast runtime. To attend these objectives, we propose a novel pin access approach and a fast design rule aware A*-interval-based path search algorithm. The pin access method uses resource sharing ghost pin access paths with dynamic legalization check. We also propose a design rule check algorithm to detect thick metal shapes that are widely created using the proposed pin access method. The path search algorithm integrates design rule check on its core, handling many design rules that would not be possible to be solved by postprocessing. It is aware of the minimum area rule, the cut spacing of via cuts within the same path, and the via library. We also present a new technique to improve A*-based path search in detailed routing. The technique makes the path search algorithm aware of the global routing guides, accelerating the search. Using ISPD 2018 Contest benchmarks, our experiments show that our router is superior to the state-of-the-art routers that were also tested using the same benchmarks. Our router has presented, on average, 77.6% less runtime, 73.5% less design rule violations, with respect to Dr. CU 2.0, which is the better of the compared routers.

References

[1]
Stefanus Mantik Posser Gracieli, Chow Wing-Kai, Ding Yixiao, and Liu Wen-Hao. 2018 Initial detailed routing contest and benchmarks. In Proceedings of the 2018 International Symposium on Physical Design (ISPD’18), 140--143.
[2]
Liu Wen-Hao, Mantik Stefanus, Chow Wing-Kai, Ding Yixiao Farshidi, Amin and Posser Gracieli. ISPD 2019 Initial detailed routing contest and benchmark with advanced routing rules. In Proceedings of the International Symposium on Physical Design (ISPD’19).
[3]
J. Cong, Jie Fang, and Kei-Yong Khoo. 2001. DUNE-a multilayer gridless routing system. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 20, 5 (2001), 633--647.
[4]
J. Cong, Jie Fang, Min Xie, and Yan Zhang. 2005. MARS-a multilevel full-chip gridless routing system. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 24, 3 (2005), 382--394.
[5]
Li Yih-Lang, Chang Yu-Ning, and Cheng Wen-Nai. 2011. A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. ACM Trans. Design Autom. Electron. Syst. 16, 2 (2011).
[6]
Li Yih-Lang, Chen Hsin-Yu, and Lin Chih-Ta. 2007. NEMO A new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 26, 4 (2007), 705--718.
[7]
Batterywala Shabbir, Shenoy Narendra, Nicholls William, and Zhou Hai. 2002. Track assignment: A desirable intermediate step between global routing and detailed routing. In Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’02), 59--66.
[8]
Zhang Yanheng and Chu Chris. 2013. RegularRoute: An efficient detailed router applying regular routing patterns. IEEE Trans. Very Large Scale Integr. Syst. 21, 9 (2013), 1655--1668.
[9]
Ozdal Muhammet Mustafa. 2009. Detailed-routing algorithms for dense pin clusters in integrated circuits. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 28, 3 (2009), 340--349.
[10]
Jia Xiaotao, Cai Yici, Zhou Qiang, and Yu Bei. 2017. A multi-commodity flow-based detailed router with efficient acceleration techniques. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 99 (2017), 1--1.
[11]
Kahng Andrew B, Wang Lutong, and Xu Bangqi. 2018. TritonRoute: An initial detailed router for advanced VLSI technologies. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18).
[12]
Sun Fan-Keng, Chen Hao, Chen Ching-Yu, Hsu Chen-Hao, and Chang Yao-Wen. 2018. A multithreaded initial detailed routing algorithm considering global routing guides. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18).
[13]
Hetzel Asmus. 1998. A sequential detailed router for huge grid graphs. In Proceedings of the Design, Automation and Test in Europe (DAC’98), 332--338.
[14]
Gester Michael, Müller Dirk, Nieberg Tim, Panten Christian, Schulte Christian, and Vygen Jens. 2013. Bonnroute: Algorithms and data structures for fast and good. ACM Trans. Design Autom. Electron. Syst. 18, 2 (2013), 1--24.
[15]
Ding Yixiao, Chu Chris, and Mak Wai-Kei. 2018. Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 37, 3 (Mar. 2018), 657--668.
[16]
Yu Hai-Juan and Chang Yao-Wen. 2018. DSA-friendly detailed routing considering double patterning and DSA template assignments. In Proceedings of the 55th ACM/ESDA/IEEE Design Automation Conference (DAC’18). 1381--1394.
[17]
Yuan Kun, Lu Katrina, and David Z. Pan. 2009. Double patterning lithography friendly detailed routing with redundant via consideration. In DAC '09 Proceedings of the 46th Annual Design Automation Conference (San Francisco 2009), ACM New York.
[18]
Gao Xin and Macchiarulo Luca. 2010. Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’10).
[19]
Mirsaeedi Minoo, Torres J. Andres, and Anis Mohab. 2011. Self-aligned double-patterning (SADP) friendly detailed routing. In Proceedings of the Design for Manufacturability through Design-Process Integration V.
[20]
Ma Qiang, Zhang Hongbo, and Martin D. F. Wong. 2012. Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In Proceedings of the 49th Annual Design Automation Conference (DAC’12).
[21]
Liu Iou-Jen, Fang Shao-Yun, and Chang Yao-Wen. 2016. Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 35, 9 (2016), 1519--1531.
[22]
Nieberg Tim. 2011. Gridless pin access in detailed routing. In Proceedings of the 48th Design Automation Conference (DAC’11), ACM, New York.
[23]
Xu Xiaoqing, Yu Bei, Gao Jhih-Rong, Hsu Che-Lun, and David Z. Pan. 2016. PARR: Pin-access planning and regular routing for self-aligned double patterning. ACM Trans. Design Autom. Electron. Syst. 21, 3 (2016).
[24]
Xu Xiaoqing, Lin Yibo, Livramento Vinicius, and David Z. Pan. 2017. Concurrent pin access optimization for unidirectional routing. In Proceedings of the 54th Annual Design Automation Conference (DAC’17).
[25]
C. Y. Lee. 1961. An algorithm for path connections and its applications. IRE Trans. Electron. Comput. 10, 3 (1961), 346--365.
[26]
Peter E. Hart, Nils J. Nilsson, and Raphael Bertram. 1968. A formal basis for the heuristic determination of minimum cost paths. IEEE Trans. Syst. Sci. Cybernet. 4, 2 (1968), 100--107.
[27]
D. Hightower. 1969. A solution to line routing problems on the continuous plane. In Proceedings of the 6th annual Design Automation Conference (DAC’69), 1--24.
[28]
Chang Fong-Yuan and Tsay Ren-Song. 2013. MANA: A shortest path maze algorithm under separation and minimum length nanometer rules. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 32, 10 (2013), 1557--1568.
[29]
Chen Gengjie, Pui Chak-Wa, Li Haocheng, Chen Jingsong, Jiang Bentian, and Evangeline F. Y. Young. 2019. Detailed routing by sparse grid graph and minimum-area-captured path search. In Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASPDAC’19), 754--760.
[30]
Ahrens Markus, Gester Michael, Klewinghaus Niko, Muller Dirk, Peyer Sven, Schulte Christian, and Tellez Gustavo. 2015. Detailed routing algorithms for advanced technology nodes. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 34, 4 (2015), 563--576.
[31]
Thomas Cormen, Charles E. Leiserson, Ronald L. Rivest, and Stein Clifford. 2002. The algorithms of Kruskal and Prim. In Introduction to Algorithms. The MIT Press, Cambridge, MA.
[32]
Li Haocheng, Chen Gengjie, Jiang Bentian, Chen Jingsong, and Evangeline F. Y. Young. 2019. Dr. CU 2.0: A scalable detailed routing framework with correct-by-construction design rule satisfaction. In Proceedings of the IEEE/ACM Inter. Conference on Computer-Aided Design (ICCAD’19).
[33]
M. M. Gonçalves Stephano, Leomar S. da Rosa Jr., and Felipe S. Marques. 2019. DRAPS: A design rule aware path search algorithm for detailed routing. IEEE Transactions on Circuits and Systems II: Express Briefs. IEEE.
[34]
Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, and Clifford Stein. 2001. Dijkstra's algorithm. In Introduction to Algorithms. MIT Press, Cambridge, MA.
[35]
Stephano M. M. Gonçalves, Leomar S. da Rosa Jr, and Felipe S. Marques. 2019. An improved heuristic function for a∗-based path search in detailed routing. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’19).
[36]
Stèphano M. M. Gonçalves, Leomar S. da Rosa Jr, and Felipe S. Marques. 2017. A survey of path search algorithms for VLSI detailed routing. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’17).

Cited By

View all
  • (2024)FastPass: A Fast Pin Access Analysis Framework for Detailed Routability EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334630243:5(1566-1579)Online publication date: May-2024
  • (2022)TritonRoute-WXL: The Open-Source Router With Integrated DRC EngineIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307926841:4(1076-1089)Online publication date: Apr-2022

Index Terms

  1. SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 26, Issue 2
    March 2021
    220 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3430836
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 23 October 2020
    Accepted: 01 August 2020
    Revised: 01 July 2020
    Received: 01 November 2019
    Published in TODAES Volume 26, Issue 2

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. A*
    2. Detailed routing
    3. ISPD 2018 Contest
    4. design rules
    5. path search
    6. pin access

    Qualifiers

    • Research-article
    • Research
    • Refereed

    Funding Sources

    • Coordenação de Aperfeiçoamento de Pessoal de Nível Superior-Brasil (CAPES)-Finance Code 001

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)22
    • Downloads (Last 6 weeks)2
    Reflects downloads up to 18 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)FastPass: A Fast Pin Access Analysis Framework for Detailed Routability EnhancementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334630243:5(1566-1579)Online publication date: May-2024
    • (2022)TritonRoute-WXL: The Open-Source Router With Integrated DRC EngineIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307926841:4(1076-1089)Online publication date: Apr-2022

    View Options

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    HTML Format

    View this article in HTML Format.

    HTML Format

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media