Physical Design for 3D Chiplets and System Integration

Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFabricTM platform, the back end packaging technology Chip-on-Wafer-on-Substrate (CoWoS®) with the integration of High-Bandwidth Memory (HBM) has been successfully deployed in high performance compute and machine learning applications to achieve high compute throughput, while Integrated Fan-Out (InFO) packaging technology is widely used in mobile applications thanks to its small footprint. System on Integrated Chips (SoIC⃨), leveraging advanced front end Silicon process technology, offers an unprecedented bonding density for vertical stacking.

Combining SoIC with CoWoS and InFO, the 3DFabric family of technologies provides a versatile and flexible platform for system design innovations. A 3DFabric design starts with system partitioning to decompose it into different functional components. In contrast to a monolithic design approach, these functional components can potentially be implemented in different technologies to optimize system performance, power, area, and cost. Then these component chips are re-integrated with 3DFabric advanced packaging technologies to form the system. There are new design challenges and opportunities arising from 3DFabric. To unleash its full potential and accelerate the product development, physical design solutions are developed. In this presentation, we will first review these advanced packaging technologies trends and design challenges. Then, we will present design solutions for 3-D chiplets and system integration.