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A program logic to verify signal temporal logic specifications of hybrid systems

Published: 19 May 2021 Publication History

Abstract

Signal temporal logic (STL) was introduced for monitoring temporal properties of continuous-time signals for continuous and hybrid systems. Differential dynamic logic (dL) was introduced to reason about the end states of a hybrid program. Over the past decade, STL and its variants have significantly gained in popularity in the industry for monitoring purposes, while dL has gained in popularity for verification of hybrid systems. In this paper, we bridge the gap between the two different logics by introducing signal temporal dynamic logic (STdL) - a dynamic logic that reasons about a subset of STL specifications over executions of hybrid systems. Our work demonstrates that STL can be used for deductive verification of hybrid systems. STdL significantly augments the expressiveness of dL by allowing reasoning about temporal properties in given time intervals. We provide a semantics and a proof calculus for STdL, along with a proof of soundness and relative completeness.

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Cited By

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  • (2025)STL and wSTL control synthesis: A disjunction-centric mixed-integer linear programming approachNonlinear Analysis: Hybrid Systems10.1016/j.nahs.2025.10157656(101576)Online publication date: May-2025
  • (2024)Using Four-Valued Signal Temporal Logic for Incremental Verification of Hybrid SystemsComputer Aided Verification10.1007/978-3-031-65633-0_12(259-281)Online publication date: 24-Jul-2024
  • (2023)Multitask Synthesis of Hybrid Systems via Temporal LogicIEEE Transactions on Automatic Control10.1109/TAC.2023.325034968:11(6883-6890)Online publication date: Nov-2023

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  1. A program logic to verify signal temporal logic specifications of hybrid systems

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        cover image ACM Conferences
        HSCC '21: Proceedings of the 24th International Conference on Hybrid Systems: Computation and Control
        May 2021
        300 pages
        ISBN:9781450383394
        DOI:10.1145/3447928
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 19 May 2021

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        Author Tags

        1. dynamic logic
        2. formal verification
        3. hybrid systems
        4. signal temporal logic

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        HSCC '21 Paper Acceptance Rate 27 of 77 submissions, 35%;
        Overall Acceptance Rate 153 of 373 submissions, 41%

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        View all
        • (2025)STL and wSTL control synthesis: A disjunction-centric mixed-integer linear programming approachNonlinear Analysis: Hybrid Systems10.1016/j.nahs.2025.10157656(101576)Online publication date: May-2025
        • (2024)Using Four-Valued Signal Temporal Logic for Incremental Verification of Hybrid SystemsComputer Aided Verification10.1007/978-3-031-65633-0_12(259-281)Online publication date: 24-Jul-2024
        • (2023)Multitask Synthesis of Hybrid Systems via Temporal LogicIEEE Transactions on Automatic Control10.1109/TAC.2023.325034968:11(6883-6890)Online publication date: Nov-2023

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