skip to main content
10.1145/3453417.3453433acmotherconferencesArticle/Chapter ViewAbstractPublication PagesrtnsConference Proceedingsconference-collections
research-article
Open access

Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling

Published: 22 July 2021 Publication History

Abstract

Multicore platforms are being increasingly adopted in Cyber -Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared system bus that connects the cores to the memory hierarchy (including caches and main memory). However, such hierarchy causes tasks running on different cores to compete for access to the shared system bus whenever data reads or writes need to be made. Such competition is problematic as it may cause variations in the execution time of tasks in a non-deterministic way. This paper presents a partitioned scheduling based approach that allows one to derive bus contention-aware worst-case response-time of tasks that follow the 3-phase task model. Experiments on synthetic task sets were performed to evaluate the effectiveness of the proposed analysis in comparison to a state-of-the-art approach. The experimental results reveal an increase of up to 34 percentage points of schedulable task sets in comparison to the compared approach.

References

[1]
Ahmed Alhammad and Rodolfo Pellizzoni. 2014. Schedulability analysis of global memory-predictable scheduling. In Proceedings of the 14th International Conference on Embedded Software - EMSOFT ’14. ACM Press, New Delhi, India, 1–10. https://doi.org/10.1145/2656045.2656070
[2]
A. Alhammad and R. Pellizzoni. 2014. Time-predictable execution of multithreaded applications on multicore systems. In 2014 Design, Automation Test in Europe Conference Exhibition (DATE). 1–6. https://doi.org/10.7873/DATE.2014.042
[3]
R. J. Bril, J. J. Lukkien, and W. F. J. Verhaegh. 2007. Worst-Case Response Time Analysis of Real-Time Tasks under Fixed-Priority Scheduling with Deferred Preemption Revisited. In 19th Euromicro Conference on Real-Time Systems (ECRTS’07). 269–279.
[4]
D. Casini, A. Biondi, G. Nelissen, and G. Buttazzo. 2020. A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 239–252. https://doi.org/10.1109/RTAS48715.2020.000-3
[5]
Sudipta Chattopadhyay, Abhik Roychoudhury, and Tulika Mitra. 2010. Modeling Shared Cache and Bus in Multi-Cores for Timing Analysis. In Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems (St. Goar, Germany) (SCOPES ’10). Association for Computing Machinery, New York, NY, USA, Article 6, 10 pages. https://doi.org/10.1145/1811212.1811220
[6]
Dakshina Dasari, Benny Akesson, Vincent Nelis, Muhammad Ali Awan, and Stefan M. Petters. 2013. Identifying the sources of unpredictability in COTS-based multicore systems. In 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE, Porto, 39–48. https://doi.org/10.1109/SIES.2013.6601469
[7]
D. Dasari, B. Andersson, V. Nelis, S. M. Petters, A. Easwaran, and J. Lee. 2011. Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus. In 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications. 1068–1075.
[8]
Dakshina Dasari, Vincent Nelis, and Benny Akesson. 2015. A framework for memory contention analysis in multi-core platforms. Real-Time Systems 52 (06 2015). https://doi.org/10.1007/s11241-015-9229-9
[9]
Robert I. Davis, Sebastian Altmeyer, Leandro S. Indrusiak, Claire Maiza and·Vincent Nelis, and Jan Reineke. 2017. An extensible framework for multicore response time analysis. Real-Time Systems (July 2017).
[10]
Guy Durrieu, Madeleine Faugère, Sylvain Girbal, Daniel Gracia Pérez, Claire Pagetti, and W. Puffitsch. 2014. Predictable Flight Management System Implementation on a Multicore Processor. In Embedded Real Time Software (ERTS’14). TOULOUSE, France. https://hal.archives-ouvertes.fr/hal-01121700
[11]
P. Emberson, R. Stafford, and R.I. Davis. 2010. Techniques For The Synthesis Of Multiprocessor Tasksets. WATERS’10 (01 2010).
[12]
T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury. 2011. Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds. In 2011 23rd Euromicro Conference on Real-Time Systems. 3–12.
[13]
C L Liu. [n.d.]. Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. ([n. d.]), 16.
[14]
Claudio Maia, Geoffrey Nelissen, Luis Nogueira, Luis Miguel Pinho, and Daniel Gracia Perez. 2017. Schedulability analysis for global fixed-priority scheduling of the 3-phase task model. In 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). IEEE, Hsinchu, Taiwan, 1–10. https://doi.org/10.1109/RTCSA.2017.8046313
[15]
Claudio Maia, Luis Nogueira, Luis Miguel Pinho, and Daniel Gracia Perez. 2016. A closer look into the AER Model. In 2016 IEEE 21st International Conference on Emerging Technologies and Factory Automation (ETFA). IEEE, Berlin, Germany, 1–8. https://doi.org/10.1109/ETFA.2016.7733567
[16]
Claire Maiza, Hamza Rihani, Juan M. Rivas, Joël Goossens, Sebastian Altmeyer, and Robert I. Davis. 2019. A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems. Comput. Surveys 52, 3 (June 2019), 1–38. https://doi.org/10.1145/3323212
[17]
Rodolfo Pellizzoni, Emiliano Betti, Stanley Bak, Gang Yao, John Criswell, Marco Caccamo, and Russell Kegley. 2011. A Predictable Execution Model for COTS-Based Embedded Systems. In 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, Chicago, IL, USA, 269–279. https://doi.org/10.1109/RTAS.2011.33
[18]
Syed Aftab Rashid, Geoffrey Nelissen, and Eduardo Tovar. 2020. Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems. https://doi.org/10.23919/DATE48585.2020.9116265
[19]
J. M. Rivas, J. Goossens, Xavier Poczekajlo, and Antonio Paolillo. 2019. Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems. In ECRTS.
[20]
J. Rosen, A. Andrei, P. Eles, and Z. Peng. 2007. Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. In 28th IEEE International Real-Time Systems Symposium (RTSS 2007). 49–60.
[21]
Simon Schliecker and Rolf Ernst. 2010. Real-time performance analysis of multiprocessor systems with shared memory. ACM Transactions on Embedded Computing Systems 10, 2 (Dec. 2010), 1–27. https://doi.org/10.1145/1880050.1880058
[22]
Gero Schwäricke, Tomasz Kloda, Giovani Gracioli, Marko Bertogna, and Marco Caccamo. 2020. Fixed-priority memory-centric scheduler for COTS-based multiprocessors. In 32nd Euromicro Conference on Real-Time Systems, ECRTS 2020(Leibniz International Proceedings in Informatics, LIPIcs), Marcus Volp (Ed.). Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. https://doi.org/10.4230/LIPIcs.ECRTS.2020.132nd Euromicro Conference on Real-Time Systems, ECRTS 2020 ; Conference date: 07-07-2020 Through 10-07-2020.
[23]
R. Tabish, R. Mancuso, S. Wasly, A. Alhammad, S. S. Phatak, R. Pellizzoni, and M. Caccamo. 2016. A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 1–11. https://doi.org/10.1109/RTAS.2016.7461321
[24]
Rohan Tabish, Renato Mancuso, Saud Wasly, Rodolfo Pellizzoni, and Marco Caccamo. 2019. A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems. Real-Time Systems 55 (10 2019). https://doi.org/10.1007/s11241-019-09340-0
[25]
K. W. Tindell, A. Burns, and A. J. Wellings. 1994. An Extendible Approach for Analyzing Fixed Priority Hard Real-Time Tasks. Real-Time Syst. 6, 2 (March 1994), 133–151. https://doi.org/10.1007/BF01088593
[26]
Gang Yao, Rodolfo Pellizzoni, Stanley Bak, Emiliano Betti, and Marco Caccamo. 2012. Memory-centric scheduling for multicore hard real-time systems. Real-Time Systems 48, 6 (Nov. 2012), 681–715. https://doi.org/10.1007/s11241-012-9158-9

Cited By

View all
  • (2024)Improved Memory Contention Analysis for the 3-Phase Task Model2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA62462.2024.00012(11-20)Online publication date: 21-Aug-2024
  • (2024)Multi-core interference over-estimation reduction by static scheduling of multi-phase tasksReal-Time Systems10.1007/s11241-024-09427-360:4(665-703)Online publication date: 5-Sep-2024
  • (2023)Improved Bus Contention Analysis for 3-Phase Tasks2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA58653.2023.00036(243-252)Online publication date: 30-Aug-2023
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
RTNS '21: Proceedings of the 29th International Conference on Real-Time Networks and Systems
April 2021
236 pages
ISBN:9781450390019
DOI:10.1145/3453417
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 July 2021

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Funding Sources

  • FCT/MCTES (Portuguese Foundation for Science and Technology)

Conference

RTNS'2021

Acceptance Rates

Overall Acceptance Rate 119 of 255 submissions, 47%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)121
  • Downloads (Last 6 weeks)15
Reflects downloads up to 20 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2024)Improved Memory Contention Analysis for the 3-Phase Task Model2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA62462.2024.00012(11-20)Online publication date: 21-Aug-2024
  • (2024)Multi-core interference over-estimation reduction by static scheduling of multi-phase tasksReal-Time Systems10.1007/s11241-024-09427-360:4(665-703)Online publication date: 5-Sep-2024
  • (2023)Improved Bus Contention Analysis for 3-Phase Tasks2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA58653.2023.00036(243-252)Online publication date: 30-Aug-2023
  • (2022)Contention-free scheduling of PREM tasks on partitioned multicore platforms2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)10.1109/ETFA52439.2022.9921531(1-8)Online publication date: 6-Sep-2022
  • (2022)Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time SystemsIEEE Access10.1109/ACCESS.2022.320370210(93799-93811)Online publication date: 2022
  • (2022)Schedulability analysis for 3-phase tasks with partitioned fixed-priority schedulingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2022.102706131:COnline publication date: 1-Oct-2022
  • (2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

HTML Format

View this article in HTML Format.

HTML Format

Login options

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media