research-article

PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis

Authors:

Weifeng LiuAuthors Info & Claims

GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSI

Pages 327 - 332

https://doi.org/10.1145/3453688.3461526

Published: 22 June 2021 Publication History

Abstract

With the increasing complexity of integrated circuits, it is becoming cumulatively challenging to solve the entire large-scale nonlinear algebraic system in DC analysis within reasonable simulation time and without accuracy lost. For this reason, we present an efficient parallel arclength approach called PALBBD to solve DC problems for large capacity and full accuracy in this paper. We process the m+1 dimensions equation of the Newton-Raphson (NR) iteration in an alternative way, which maintains the Jacobian matrix structure. Besides, we exploit the bordered block diagonal (BBD) form to save the matrix for parallel computing. Moreover, we check the convergence of each sub-partition and bypass the calculations of converged ones to reduce the amount of unnecessary computations during the iteration. In order to ensure the accuracy, we use a correction equation to replace the Schur complement updating for the bypassed sub-partitions. The proposed PALBBD is implemented and integrated to the SPICE simulator and verified by 72 real-world circuits. It outperforms the conventional serial arclength method with up to 73.93X speedup and 45% bypass ratio.

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Cited By

Jiang JDuan YJin ZNakamura YWang Y(2025)Boosting the Performance of Transistor-Level Circuit Simulation with GNNProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703149(114-120)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703149
Jin ZFeng TWu XNiu DZhou ZZhuo C(2024)MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546783(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546783
Dong YNiu DJin ZZhang CLi QSun C(2023)Adaptive Stepping PTA for DC Analysis Based on Reinforcement LearningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2022.320735670:1(266-270)Online publication date: Jan-2023
https://doi.org/10.1109/TCSII.2022.3207356
Show More Cited By

Index Terms

PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis
1. Hardware
  1. Electronic design automation
    1. Methodologies for EDA
      1. Software tools for EDA

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Published In

GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSI

June 2021

504 pages

ISBN:9781450383936

DOI:10.1145/3453688

General Chairs:
Yiran Chen
Duke University, USA
,
Victor Zhirnov
Semiconductor Research Corporation, USA
,
Program Chairs:
Avesta Sasan
George Mason University, USA
,
Ioannis Savidis
Drexel University, USA

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Published: 22 June 2021

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Presentation Video https://dl.acm.org/doi/10.1145/3453688.3461526#GLSVLSI21-glsv088p.mp4

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GLSVLSI '21: Great Lakes Symposium on VLSI 2021

June 22 - 25, 2021

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Cited By

Jiang JDuan YJin ZNakamura YWang Y(2025)Boosting the Performance of Transistor-Level Circuit Simulation with GNNProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703149(114-120)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703149
Jin ZFeng TWu XNiu DZhou ZZhuo C(2024)MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546783(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546783
Dong YNiu DJin ZZhang CLi QSun C(2023)Adaptive Stepping PTA for DC Analysis Based on Reinforcement LearningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2022.320735670:1(266-270)Online publication date: Jan-2023
https://doi.org/10.1109/TCSII.2022.3207356
Niu DDong YJin ZZhang CLi QSun C(2023)OSSP-PTA: An Online Stochastic Stepping Policy for PTA on Reinforcement LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325173142:11(4310-4323)Online publication date: 2-Mar-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3251731
Chen YPei HDong XJin ZZhuo CWang T(2022)Application of Deep Learning in Back-End Simulation: Challenges and OpportunitiesProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712511(641-646)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712511

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