Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs

Negative Capacitance FET (NCFET) is one of the most promising variants of the emerging steep-slope transistors, able to overcome the ?Boltzmann limit'. The ferroelectric layer in the gate stack brings in new dynamics to the transistor operation by amplifying the surface potential. Steeper subthreshold slope, higher ON/OFF ratio, and the possibility to attain negative output conductance provide unique opportunities for NCFET-based circuit design. However, NCFETs inherently possess additional sources of variation, and hence, the promise of performance benefits in the nominal designs must be examined through extensive variation analysis. The non-volatile ferroelectric FETs (FEFETs) are promising candidates for storage-class memory, whereas the volatile NCFETs are suitable for high-speed SRAM design. In this work, we first draw a contrast between the modeling approaches ideal for the non-volatile FEFETs and volatile NCFETs. We then utilize a compact model for NCFET to analyze the design possibilities in an NCFET-based 6-T SRAM cell compared with its conventional counterpart ? both implemented in the 10 nm technology node. We examine the read, write, and hold performance of the SRAM cells through Monte Carlo variation analysis. We show that, even with additional variation induced spread in the device characteristics, NCFET-based SRAM cell can achieve better Static Noise Margin (SNM) during read/hold modes and allows more aggressive supply voltage scaling. The increased hold stability imposes a penalty in the write performance ? forcing design trade-offs.