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Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Published: 03 November 2021 Publication History

Abstract

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

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    Published In

    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 18, Issue 1
    January 2022
    497 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/3483339
    • Editor:
    • Ramesh Karri
    Issue’s Table of Contents
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    Publication History

    Published: 03 November 2021
    Accepted: 01 May 2021
    Revised: 01 March 2021
    Received: 01 October 2020
    Published in JETC Volume 18, Issue 1

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    Author Tags

    1. Monolithic 3D IC
    2. design-for-test

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    • (2024)A Scan-Chain-Based Built-in Self-Test for ILV in Monolithic 3-D ICsIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2024.347278773(1-13)Online publication date: 2024
    • (2023)Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.322885031:3(296-309)Online publication date: 1-Mar-2023
    • (2022)Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00019(118-127)Online publication date: Sep-2022
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