skip to main content
10.1145/3464432.3464434acmotherconferencesArticle/Chapter ViewAbstractPublication PagesprogrammingConference Proceedingsconference-collections
research-article

Improving on the Experience of Hand-Assembling Programs for Application-Specific Architectures

Published: 21 August 2021 Publication History

Abstract

Creating an application-specific processor is an effective and popular way to solve many problems in embedded hardware design using FPGAs, ASICs, or custom silicon. Programming these processors is complicated by the lack of toolchain support for creating the necessary binary code as part of hardware design, implementation, and evaluation. Hardware developers who cannot create their own ad-hoc assembler are left to hand-assemble their code into binary instructions which is both painful and error prone. We present a tool that supports the rapid creation of assemblers for application-specific processors. A single language is used to specify both instruction formats as collections of bit fields and the instantiation of those formats into sequences of binary instructions as a single, homogeneous activity that is designed to be as familiar and accessible to hardware designers as possible. The output from the tool can be used directly by hardware synthesis tools to initialise the program memory of an application-specific processor.

References

[1]
Achronix 2018. FPGA Accelerator Cards. Achronix. https://www.achronix.com/ (accessed 2020/03/17).
[2]
Bryan Ford. 2004. Parsing expression grammars: a recognition-based syntactic foundation. In POPL ’04: Proceedings of the 31st ACM SIGPLAN-SIGACT symposium on Principles of programming languages (Venice, Italy). ACM Press, 111–122. https://doi.org/10.1145/964001.964011
[3]
Andrew Greenberg. 2011. Crypto Currency. https://www.forbes.com/forbes/2011/0509/technology-psilocybin-bitcoins-gavin-andresen-crypto-currency.html(accessed 2020/03/17).
[4]
Y. LeCun, Y. Bengio, and G. Hinton. 2015. Deep learning. In Nature, Vol. 521. 436–444. https://doi.org/10.1038/nature14539
[5]
Nandland.com. [n.d.]. UART in VHDL and Verilog. https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html(accessed 2020/03/17).
[6]
Colm Networks. 2019. Ragel State Machine Compiler. http://www.colm.net/open-source/ragel/ (accessed 2020/03/17).
[7]
Ian Piumarta. 2016. peg/leg— recursive-descent parser generators for C. https://www.piumarta.com/software/peg/ (accessed 2020/03/17).
[8]
Justin Rajewski. 2018. Basic CPU. Alchitry. https://alchitry.com/blogs/tutorials/basic-cpu?_pos=1&_sid=69d5af85b&_ss=r(accessed 2020/03/17).
[9]
RISC-V. 2020. Specifications. https://riscv.org/technical/specifications (accessed 2020/03/17).
[10]
Robert Sedgewick and Kevin Wayne. 2016. Computer Science: An Interdisciplinary Approach. Addison-Wesley Professional, Chapter 6, 873–984. ISBN 978-0134076423 https://introcs.cs.princeton.edu/java/60machine (accessed 2020/03/17).
[11]
Mark Smotherman. 2019. A Brief History of Microcode. https://people.cs.clemson.edu/~mark/uprog.html (accessed 2020/03/17).
[12]
Synopsis. 2021. ASIP Designer. https://www.synopsys.com/dw/ipdir.php?ds=asip-designer(accessed 2020/03/17).
[13]
Wikipedia. 2021. PicoBlaze — external links. https://en.wikipedia.org/wiki/PicoBlaze#External_links(accessed 2020/03/17).
[14]
Xilinx, Inc.2019. 7 Series FPGAs Memory Resources. https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf(accessed 2020/03/17).
[15]
Xilinx, Inc.2020. 7 Series FPGAs Data Sheet: Overview. https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf(accessed 2020/03/17).

Cited By

View all
  • (2023)Design and Implementation of a Compiler Supporting RISC-V Custom Cryptographic and Vector InstructionsProceedings of the 7th International Conference on Computer Science and Application Engineering10.1145/3627915.3628090(1-7)Online publication date: 17-Oct-2023

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
Programming '21: Companion Proceedings of the 5th International Conference on the Art, Science, and Engineering of Programming
March 2021
76 pages
ISBN:9781450389860
DOI:10.1145/3464432
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 August 2021

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. FPGA configuration memory
  2. application specific processor implementation
  3. domain specific languages
  4. embedded programming
  5. macro languages
  6. micro assemblers
  7. microcode

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Conference

<Programming> '21

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)5
  • Downloads (Last 6 weeks)0
Reflects downloads up to 05 Mar 2025

Other Metrics

Citations

Cited By

View all
  • (2023)Design and Implementation of a Compiler Supporting RISC-V Custom Cryptographic and Vector InstructionsProceedings of the 7th International Conference on Computer Science and Application Engineering10.1145/3627915.3628090(1-7)Online publication date: 17-Oct-2023

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

HTML Format

View this article in HTML Format.

HTML Format

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media